Tomasz Szumlak

Performance of the LHCb vertex detector alignment algorithm determined with beam test data

Reference EPFL-ARTICLE-154459doi:10.1016/j.nima.2008.07.154View record in Web of Science Record created on 2010-11-05, modified on 2017-05-12

First Beam Test Characterisation of a 3D-stc Silicon Short Strip Detector

The planned upgrade to the CERN Large Hadron Collider (LHC), the Super-LHC (sLHC) will increase its luminosity by a factor of ten. This necessitates the development of silicon tracking detectors that are significantly more radiation resistant than the ones employed at the LHC. Currently, new detector technologies are being developed to cope with the increased levels of radiation damage at the sLHC. A possible radiation hard option for silicon short strip devices (SSD) in the inner layers of sLHC trackers are 3-D detectors with rows of columnar electrodes processed into the bulk material. These are joined together to form strips. While the excellent radiation hardness of this design has been proven before in lab experiments, a 3-D SSD prototype has now been investigated for the first time in a beam test with pions of a nominal energy of 180 GeV. The use of analog LHC-speed electronics, a beam telescope and time-resolved measurements allowed for detailed studies of the signal behavior on the hit strip and its neighboring strips. Charge collection and efficiency were as well measured with respect to time and point of incidence of the beam particles on the detector. The results of these measurements are presented in this paper.

VETRA - offline analysis and monitoring software platform for the LHCb Vertex Locator

The LHCb experiment is dedicated to studying CP violation and rare decay phenomena. In order to achieve these physics goals precise tracking and vertexing around the interaction point is crucial. This is provided by the VELO (VErtex LOcator) silicon detector. After digitization, FPGAs are employed to run several algorithms to suppress noise and reconstruct clusters. This is performed by an FPGA based processing board. An off-line software project, VETRA, has been developed which performs a bit perfect emulation of this complex processing in the FPGAs. This is a novel development as this hardware emulation is not standalone but rather is fully integrated into the LHCb software to allow the reconstruction of full data from the detector. This software platform facilitates the development and understanding of the behaviour of the processing algorithms, the optimization of the parameters of the algorithms that will be loaded into the FPGA and monitoring of the detector performance. This framework has also been adopted by the Silicon Tracker detector of LHCb. This processing framework was successfully used with the first 1500 tracks of data in the VELO obtained from the first LHC beam in September 2008. The software architecture and utilisation of the VETRA project will be discussed in detail.