Tomoyuki Hatakeyama

Electro-Thermal Behavior of a Sub-Micrometer Bulk CMOS Device: Modeling of Heat Generation and Prediction of Temperatures

The electro-thermal behavior of a bulk CMOS device is analyzed using the hydrodynamic model equation. The analysis is first applied to an introductory example of a single field-effect-transistor (FET) to indicate the importance of incorporating a non-equilibrium state between charge carriers and phonons in the analytical model. Then, the system of hydrodynamic model equations is described in detail, which takes into account carrier generation/recombination process and non-equilibrium between charge carriers and phonons. A supposed bulk CMOS device has nano-meter dimensions and thus is vulnerable to malfunction due to crosstalk between the constituent FETs. The simulation of electro-thermal transients in the entire CMOS domain is performed focusing on the behavior in a short period after switching of the gate voltage from low to high. The result shows a significant level of crosstalk that may lead to impairment of the switching function of the CMOS. Also shown is the development of a hot spot at the source region of the activated FET in addition to the one at the gate/drain corner. The deliberate omission of sub-continuum mechanisms, particularly the carrier generation/recombination, from the analytical model produced erroneous distributions of charge carrier density and temperature, thus proving the significance of this mechanism in defining heat generation and heat flow in the device.

Analysis of hot spot temperature in power Si MOSFET with electro-thermal analysis

In recent years, electronics has been downsizing, and thermal problem becomes more serious. Therefore, more accurate thermal design is required for improvement of electronics reliability. For more accurate thermal design, we should consider temperature distribution of a chip. In a chip, a lot of semiconductor devices are mounted. Therefore, to investigate temperature distribution of a chip, temperature distribution of a semiconductor device should be obtained. Power Si MOSFET is widely used in car electronics as a semiconductor device. However, the thermal properties of power Si MOSFET are not clear. Therefore, we focus on power Si MOSFET, and discuss thermal properties using electro-thermal analysis. The calculation results show a hot spot appears in power Si MOSFET, and the hot spot temperature is higher with increase in applied voltage. Furthermore, the appearance position of the hot spot is almost the same in any analysis condition when applied voltage is changed.

Application of Thermal Network Model to Transient Thermal Analysis of Power Electronic Package Substrate

In recent years, there is a growing demand to have smaller and lighter electronic circuits which have greater complexity, multifunctionality, and reliability. High-density multichip packaging technology has been used in order to meet these requirements. The higher the density scale is, the larger the power dissipation per unit area becomes. Therefore, in the designing process, it has become very important to carry out the thermal analysis. However, the heat transport model in multichip modules is very complex, and its treatment is tedious and time consuming. This paper describes an application of the thermal network method to the transient thermal analysis of multichip modules and proposes a simple model for the thermal analysis of multichip modules as a preliminary thermal design tool. On the basis of the result of transient thermal analysis, the validity of the thermal network method and the simple thermal analysis model is confirmed.

Impact of the computational boundary on the coupled thermal and electrical analysis of Si devices

Numerical calculation of submicron silicon MOSFET and surrounding region is performed. Conjugate nature of the thermal and electrical behavior in the device is considered, and the lattice temperature is solved as well as the electron concentration and the electron temperature. Considering both the electron temperature and the lattice temperature is important for the device modeling, for example the electron distribution shows the difference with and without considering the electron temperature. In this research, by extending analysis region, we examine the influence of the computational boundary; this is the first step of modeling the actual device (CMOS structure). The calculated results show the importance of considering not only silicon MOSFET but also surrounding region; the surrounding region has a significant impact on the calculated current density of the source and drain electrode, the maximum lattice temperature and the maximum electron temperature. We discuss the conjugate nature of the thermal and electrical behavior of actual silicon devices for modeling.

Electro-Thermal Analysis of Submicron Si MOSFET With Zoned Mesh Based on Semiconductor Physics Theory

The results of electro-thermal analysis, which is widely known as hydrodynamic model, are strongly dependent on the mesh size of model. However, the theory and method of accurate mesh size have not been investigated. In this research, we focus on submicron Si MOSFET and show the mesh zoning method for electro-thermal analysis. First, we explain the mesh zoning method for vertical direction, i.e. the direction from the gate oxide to the bottom surface of MOSFET, which was derived from the theory of the semiconductor physics, because the calculation results were strongly dependent on the mesh size of vertical direction. Along the vertical direction, Debye length with consideration of submicron size is the most important length scale. This Debye length is not same to the conventional one. We briefly show the derivation procedure of Debye length considered submicron phenomena and the procedure of the mesh zoning method by using this Debye length. Then, we show the error of the calculation results depended on the mesh size for the lateral direction, i.e. direction from the source electrode to the drain electrode, and we investigate the most important part in MOSFET for precise calculation.Copyright

Effect of the Device Structure in Electro-Thermal Analysis of Si CMOS

Numerical calculation of submicron silicon MOSFET and CMOS device is performed. In order to have a higher degree of integration, the distance between two MOSFETs in CMOS structure can be decreased. But decreasing the distance between two MOSFETs results in an electrical interaction. In this research, by comparing the calculation result of n-type and p-type MOSFET and that of CMOS, we examine the interaction mechanism between n-type and p-type MOSFET in CMOS device when the distance between n-type and p-type MOSFET is decreased. From the calculated results, we investigate that the reason of the interaction between two MOSFET in CMOS is the forward bias at the p-n junction of substrate. Furthermore, we can estimate the distance, at the case of interaction, from the results of n-type and p-type MOSFET separately model, not from the results of CMOS model.Copyright

Investigation of Device Interactions Between Two MOSFETs in Si CMOS

Experimental works about the device interactions between nMOS and pMOS in bulk Si CMOS were performed. In the bulk Si CMOS, in the case that the distance between two MOSFETs is not enough, it is important to consider the risk of the device interactions between nMOS and pMOS. In this work, we fabricated bulk Si CMOS, in which the distance between pMOS and nMOS can be variable. And we observed the characteristics of the device operation by using fabricated CMOS under the dc bias condition. In this research, we focused on the leakage current between two MOSFETs in CMOS inverter depending on the distance between two MOSFETs, applied voltage and temperature. Experimental results showed that our fabricated CMOS shows quite small leakage current and the leakage current is less than 1% compared to CMOS on state current even with small distance between two MOSFETs at the high voltage condition and the high temperature condition.Copyright

Temperature and Time Dependence of Device Interactions in Submicron Si CMOS

Numerical calculation of submicron Si CMOS was performed. The electro-thermal analysis, which is known as hydrodynamic model, is applied to bulk CMOS structure. In this research, we analyze the temperature and time dependence of device interactions in submicron bulk Si CMOS. The width and thickness of the insulator between nMOS and pMOS are changed and the device interaction between nMOS and pMOS are considered. The calculation results show that using thicker insulator between two MOSFETs makes it possible to utilize shorter width of the insulator. Furthermore, the results, which the substrate temperature are changed from 350K to 400K, show that the higher substrate temperature cause the delay of the device interactions in CMOS.

Electro-thermal analysis of device interactions in Si CMOS structure

Numerical calculation of submicron silicon MOSFET and CMOS device is performed. Conjugate nature of the thermal and electrical behavior in the device is considered, and the lattice temperature is solved as well as the electron concentration and the electron temperature. Considering both the electron temperature and the lattice temperature is important for the device modeling, for example the electron distribution shows the difference with and without considering the electron temperature. In this research, by comparing the calculation result of n-type and p-type MOSFET and that of CMOS, we examine the interaction mechanism between n-type and p-type MOSFET in CMOS device when the distance between n-type and p-type MOSFET is decreased. From the calculated results, we investigate that the reason of the interaction between two MOSFET in CMOS is the forward bias at the p-n junction of substrate. Furthermore, we can estimate the distance, at the case of interaction, from the results of n-type and p-type MOSFET separately model, not from the results of CMOS model.

On the modelling of electrons in thermo-electronic modelling of Si MOSFETs

Importance of the modeling of electrons in coupled electro-thermal analysis of Si MOSFETs is discussed. The simple, lumped-electron temperature model predicts drastic increase of the electron temperature above the electric field of the order of 10/sup 6/V/m. Also, the calculation of electron thermal conductivity predicts that the thermal conductivity reaches on the order of 10/sup -1/ W/m-K. Numerical calculation of coupled electrical and thermal analysis predicts 10/sup 3/ K order of temperature gradient in the channel region. These results clearly exhibit the importance of the modeling of electrons in the coupled analysis.