Tomyslav Sledevic

FPGA based fast Lithuanian isolated word recognition system

The article presents the Lithuanian isolated word recognition system implementation in a FPGA hard-core. The pursued objective is the acceleration of the previous soft-core implementation at both key stages: feature extraction and recognition. The 12-th order cepstral analysis is used to extract speech signal features, while for isolated word recognition a dynamic time warping is used. Implementation completely done in the VHDL hard-core allowed us to 320 times speed-up the signal cepstrum calculation and 348 times - one dynamic time warping comparison with border constraints. The recognition system works in real time and is built on medium class FPGA, operating at 50 MHz main clock frequency. It is tested on 6 times repeated 100 Lithuanian words dictionary. Speaker dependent recognition tests done for 10 speakers yield the 97.7 % average recognition accuracy (with 4.9 % recognition improvement over the previous implementation).

The lattice-ladder neuron and its training circuit implementation in FPGA

FPGA implementation of a lattice-ladder multilayer perceptron structure together with its training algorithm in a full scale seems attractive, however there is a lack of preliminary results on the choice of implementation architecture. The aim of this investigation was to get insights on the selected neuron model fixed-point architecture (necessary to use word length) and its complexity (required number of LUT and DSP slices and BRAM size) by the evaluation of the reproduced by lattice-ladder neuron accuracy of bandwidth and central frequency as also as output signal normalized mean error. Thus the second order fixed-point normalized lattice-ladder neuron with its training algorithm was implemented in Artix-7 FPGA. The experiments were performed using various bandwidths and word length constrains. In general increase of word length yielded smaller mean errors. However the limited size BRAM used for trigonometric function LUTs was a bottleneck to improve the precision while doubling the number of DSP slices.

Word Recognition Acceleration by Double Random Seed Matching in Perceptual Cepstrum Error Space

Paper presents an algorithm for acceleration of the dynamic time warping (DTW) based isolated word recognition algorithm. The number of matching operations directly depends on the size of vocabulary. A set of perceptual cepstrum features is calculated for each word and stored in the vocabulary as a reference. Additionally all words (references) are compared between each other using DTW in order to get the reference-to-reference matches. The acceleration of pattern matching is acquired by adaptive search of the pattern reference according to the previous matching results ant reference-to-reference matches. A modified word selection scenario applied for the vocabulary reduces the number of matching operations by 62-70 % in average. The reduction of matching operations allows to use DTW based speech recognition methods in real-time control applications and only need additional 13 % of vocabulary storage space.

Towards optimal FPGA implementation of lattice-ladder neuron and its training circuit

The FPGA implementation of lattice-ladder multilayer perceptron with its training algorithm seems attractive, however there is a lack of experimental results on its efficiency. The main aim of this investigation was to optimize the latency and DSP block usage for the normalized lattice-ladder neuron (LLN) and its simple gradient training algorithm implementation on FPGA. Four alternative regressor lattices to be used in LLN training were considered and experimentally evaluated. The optimal resource sharing was approached by the LLN data flow graph partitioning into DSP block subgraphs. The experiments were performed by varying the number of synapses and the order of lattice-ladder filters. Recommendations for particular LLN implementation cases were given.

FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron

FPGA implementation of hyperbolic tangent activation function for multilayer perceptron structure seems attractive; however, there is a lack of preliminary results on the choice of memory size particularly, when LUT of the function is stored in dedicated on-chip block RAM. The aim of this investigation was to get insights on the distortions of the selected neuron model output by the evaluation of transfer function RMS error and neuron output signal mean and maximum errors while changing the gain and memory size of the activation function. Thus, the range addressable activation function for the second order normalized lattice-ladder neuron was implemented in Artix-7 FPGA. Various gain and memory constrains were investigated. The increase of LUT memory size and gain yielded smaller error of output signal and nonlinear influence on the transfer function. 2 kB of BRAM is sufficient to achieve tolerable less than 0.4 % maximum error utilizing only 0.36 % of total on-chip block memory. DOI: http://dx.doi.org/10.5755/j01.eie.22.2.14598

The evaluation of configurable core for disparity map computation based on FPGA

The article presents the evaluation of configurable hard-core for disparity map computation based on FPGA. The proposed hardware architecture performs the computation of disparity map in a pipelined order. The local block matching based on sum of absolute differences is performed for the search of corresponding similarities in two stereo images. The disparity core is implemented on Virtex-4, Artix-7, Kintex-7 FPGAs and the corresponding results on required resources and performance are presented. The core was evaluated under: VGA, HD720 and HD1080 formats of video stream, local block sizes from 4 × 4 to 32 × 32 pixels and maximal disparity ranges from 32 up to 512 pixels. The results show that using xc4vsx35 FPGA the maximal frame rates are 224, 75 and 33 frames per second for VGA, HD720 and HD1080 video formats, respectively.

Alternative implementations of metabolic P system in FPGA

Metabolic P (MP) system formalism is already proven to be applicable and useful in various fields of science, however knowledge about possibilities of MP system implementation in a hardware is limited. The use of a reconfigurable hardware empowers investigation in a search of the best implementation strategy for specified computing. Thus in the paper FPGA implementation techniques for MP systems were examined and compared. The MP system that models the process of Glucose-Insulin interactions in the intravenous glucose tolerance test was used in the study. It was implemented in FPGA by the use of three alternative FPGA implementation techniques: single process, single DSP slice and pipelined implementation. Experimental results together with suggested evaluation metrics were estimated. It was shown that single DSP slice implementation is preferable if minimal FPGA resource utilization is required, while pipelined technique use yields MP system that has a better balance between operating frequency and latency.