Ton Engbersen

Fast and scalable packet classification

Emerging Internet applications create the need for advanced packet classifiers. We propose a novel multifield classification scheme, called P/sup 2/C, which exploits the strengths of state-of-the-art memory technologies to provide wire-speed classification performance for OC-192 and beyond, in combination with very high storage efficiency and the support of fast incremental updates. Key features of the new scheme are its ability to adapt to the complexity of a classification rule set, whereas the storage requirements and update dynamics can be tuned at the granularity of individual rules. This makes P/sup 2/C suitable for a broad spectrum of applications.

Technologies and building blocks for fast packet forwarding

We provide a review of the state of the art and the future of packet processing and switching. The industrys response to the need for wire-speed packet processing devices whose function can be rapidly adapted to continuously changing standards and customer requirements is the concept of special programmable network processors. We discuss the prerequisites of processing tens to hundreds of millions of packets per second and indicate ways to achieve scalability through parallel packet processing. Tomorrows switch fabrics, which will provide node-internal connectivity between the input and output ports of a router or switch, will have to sustain terabit-per-second throughput. After reviewing fundamental switching concepts, we discuss architectural and design issues that must be addressed to allow the evolution of packet switch fabrics to terabit-per-second throughput performance.

A combined input and output queued packet switched system based on PRIZMA switch on a chip technology

A packet-switched system architecture based on the combination of a single-chip output-buffered switch element and input queues that sort arriving packets on a per-output-port basis is proposed. Scheduling is performed in a distributed two-stage approach. Independent arbiters at each of the inputs resolve input contention. Whereas the output-buffered switch element resolves output contention. As a result of this distribution of functionality, complexity of the input arbiters is only linearly proportional to the number of output ports N, thus offering better scalability than purely input-buffered approaches that require complex centralized schedulers. Since the input queues are used as the main buffering mechanism, only a relatively small amount of memory (on the order of N/sup 2/ packet locations) is required in the shared-memory switch, allowing high-throughput implementations. We present simulation results to demonstrate the high performance and robustness under bursty traffic achieved with the proposed system architecture. A practical implementation in the form of the PRIZMA family of switch chips is outlined, with emphasis on its versatility in scaling in terms of both port speed and number of ports, and its support for quality-of-service mechanisms.

Design issues in next-generation merchant switch fabrics

Packet-switch fabrics with widely varying characteristics are currently deployed in the domains of both communications and computer interconnection networks. For economical reasons, it would be highly desirable that a single switch fabric could accommodate the needs of a variety of heterogeneous services and applications from both domains. In this paper, we consider the current requirements, technological trends, and their implications on the design of an ASIC chipset for a merchant switch fabric. We then identify the architecture upon which such a suitable and generic switch fabric could be based, and we present the general characteristics of an implementation of this switching fabric within the bounds of current state-of-the-art technology. To our knowledge, this is the first attempt to design a chipset that can be used for both communications and computer interconnection networks.

Failure Analysis of Virtual and Physical Machines: Patterns, Causes and Characteristics

In todays commercial data centers, the computation density grows continuously as the number of hardware components and workloads in units of virtual machines increase. The service availability guaranteed by data centers heavily depends on the reliability of the physical and virtual servers. In this study, we conduct an analysis on 10K virtual and physical machines hosted on five commercial data centers over an observation period of one year. Our objective is to establish a sound understanding of the differences and similarities between failures of physical and virtual machines. We first capture their failure patterns, i.e., the failure rates, the distributions of times between failures and of repair times, as well as, the time and space dependency of failures. Moreover, we correlate failures with the resource capacity and run-time usage to identify the characteristics of failing servers. Finally, we discuss how virtual machine management actions, i.e., consolidation and on/off frequency, impact virtual machine failures.

Dynamic multi-field packet classification

Emerging Internet applications create the need for advanced packet classifiers. This paper investigates the mechanisms that determine the performance of state-of-the-art multi-field classification methods, and proposes a novel scheme called P/sup 2/C for packet classification at OC-192 and OC-768 speeds. P/sup 2/C combines the strengths of embedded memory and ternary CAM technologies to achieve very high storage efficiency while maintaining fast incremental updates. Key feature of the new scheme Is Its ability to adapt to the complexity of a classification rule set, while providing effective control over the update dynamics and storage requirements at the granularity of individual rules. This makes P/sup 2/C suitable for a broad range of applications.

A robust switch architecture for bursty traffic

A novel way of building switch system architectures, based on the combination of an output-buffered switch with input queues that sort arriving packets on a per-output-port basis, is proposed that has a scheduling complexity of O(N). Simulation results to demonstrate the high and robust performance achieved with the proposed system architecture are presented, and a practical implementation is outlined.

Review of advances in neural networks

This review provides a high-level synthesis of significant recent advances in artificial neural network research, as well as multi-disciplinary concepts connected to the far-reaching goal of obtaining intelligent systems. We assume that a global outlook of these interconnected fields can benefit researchers by providing alternative viewpoints. Therefore, we present different network and neuron models, we discuss model parameters and the means to obtain them, and we draw a quick outline of information encoding, before proceeding to an overview of the relevant learning mechanisms, ranging from established approaches to novel ideas. We specifically focus on comparing the classical artificial model with the biologically-feasible spiking neuron, and we take this comparison further into a discussion on the biological plausibility of various learning approaches.

Shared memory switching + virtual output queuing: A robust and scalable switch

A novel combination of shared memory switching and virtual output queuing yields an architecture that addresses the exponential growth of the Internet. Superior scalability is achieved using distributed schedulers compared to crossbar-based fabrics requiring a central scheduler. Performance is excellent and robust. We describe the system view, an actual implementation, performance simulations for several traffic classes, and QoS results using bandwidth management.

Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation

The Square Kilometre Array (SKA) is a future radio telescope, currently being designed by the worldwide radio-astronomy community. During the first of two construction phases, more than 250,000 antennas will be deployed, clustered in aperture-array stations. The antennas will generate 2.5 Pb/s of data, which needs to be processed in real time. For the processing stages from A/D conversion to central correlation, we propose an ASIC solution using only three chip architectures. The architecture is scalable - additional chips support additional antennas or beams - and versatile - it can relocate its receiver band within a range of a few MHz up to 4GHz. This flexibility makes it applicable to both SKA phases 1 and 2. The proposed chips implement an antenna and station processor for 289 antennas with a power consumption on the order of 600W and a correlator, including corner turn, for 911 stations on the order of 90 kW.