Toni Itkonen

Modeling and Analysis of the Dead-Time Effects in Parallel PWM Two-Level Three-Phase Voltage-Source Inverters

This paper addresses modeling and analysis of the dead-time effects in parallel pulsewidth-modulated (PWM) two-level three-phase inverters. The main objective is to gain understanding of how the effects caused by the necessary blanking time, the finite turn-on and turn-off times of the switching devices, and the forward voltage drops of the switching devices and the antiparallel diodes, i.e., the dead-time effects, influence the circulating current generation between the parallel-connected units. To meet this objective, a circulating current model taking these effects into account is developed for the parallel connection of n units. The model, which is an average model by nature, can be used to study the circulating current behavior with different types of PWM methods and to estimate the resulting circulating current values when there are differences in the dead-time effect parameters. In other words, the model provides an analytical way to consider the significance of these effects. To verify the validity of the developed model, the circuit simulation and experimental results are shown and compared with the analytical results. The illustrations show that the results obtained with the developed model are in good agreement with the circuit simulations and the experiments.

Switching effects in directly paralleled three-phase AC/DC/AC converters with separate DC links

This paper analyzes the effects of asynchronous switchings in the case of directly paralleled three-phase AC/DC/AC converters. Unlike in the most previous papers, DC links of the converters are kept separate. Because of this, a path to a zero-sequence circulating current is not formed between the inverters or the rectifiers. However, it is shown that the three-phase currents may contain zero-sequence components. This is a consequence of a current circulating through the converter units. It is also shown that this kind of a circulating current may overcharge the DC link capacitors. In addition to the circulating current, a cross current flows between the inverters because of asynchronous switchings. The formation of both the cross current and circulating current paths is illustrated in detail. Simulation results are presented to validate the discussion about cross currents, circulating currents, and the capacitor charging effect.

Equal load sharing modulation technique for series-connected H-bridge multilevel converters

A modulation scheme for multilevel inverters, which ensures equal loading of the power modules is presented. The scheme uses two-to-three transformation to calculate duty-cycles of each phase directly from the reference vector expressed in the Cartesian coordinate system. There is no need for trigonometric functions, which makes the applicability of the algorithm very effective in a DSP or an FPGA. The pulse formation with module circulation is also introduced. The module circulation ensures equal load sharing and balanced DC-link voltages. The methods are verified with simulations and with experimental tests on a seven-level 100 kVA, 3 kV prototype induction motor drive.

Time-stamping-based synchronization of power electronics building block systems

Integrated design has become a very attractive choice for modern power electronic systems. One way to introduce modularity to integrated designs is to utilize intelligent power electronics building blocks as a base for power electronics systems. The main reason for moving toward a building-block-based design is that the traditional centralized control structure does not provide much flexibility and reusability. A building-block-based design needs a distributed control scheme that sets new challenges to system design. Distributed control of building blocks requires a deterministic, real-time communication scheme and accurate synchronization. The synchronization becomes an issue especially with ring-based control topologies. In this paper, a flexible time-stamping-based synchronization scheme for a cascaded ring communication topology is proposed. Further, a communication scheme suitable for building-block-based designs is presented. The achieved synchronization accuracy is analyzed in relation to a parallel connection of power semiconductors.

Switching-function-based simulation model for three-phase voltage source inverter taking dead-time effects into account

In this paper, a switching-function-based simulation model for a three-phase two-level voltage source inverter is developed. A novelty of this paper is the description how dead-time effects, caused by the necessary blanking-time, can be taken into account in the switching-function-based model. The proposed method makes it possible to study how the dead-time effects affect the behavior of the system without using simulation models constructed from ideal or detailed device models. Dead-time effects are taken into account by introducing a virtual gating signal that represents the time intervals during which both the upper and lower gating signals are off. The switching function during the blanking-time is then obtained by multiplying the virtual gating signal with the sign of the phase current. The simulation results from a single inverter system and a parallel inverter system are shown and compared with the simulation results obtained from the ideal device models to verify the validity of the developed models.

Active motor terminal overvoltage mitigation method for parallel two-level voltage source inverters

Inverter-fed motor drives can be subject to transient overvoltage problems caused by switching operations. Motor terminal overvoltages may occur if a motor is fed through a long motor cable. These overvoltages may result in a premature motor insulation failure. The phenomenon exists whether the motor is fed by a single inverter or parallel inverters. A modulation strategy and a parallel inverter topology that mitigate the motor terminal overvoltages are presented in this paper. The topology consists of parallel inverters with a common point of connection at the motor terminals. The proposed method does not use any passive filters. Experimental measurements were conducted with standard industry frequency converters to verify the method. Modulation sequences resulting in smallest possible overvoltage for two and three parallel inverters applying the method were found.

Parallel Connected Voltage Source Inverters without Intermodule Reactors

Connecting power converters in parallel is useful method for solving high power requirements. Parallel structure without intermodule reactors would be desirable because of its low cost and compact size. Due to the finite tolerances in power stages and delays in control circuits, switchings of the parallel connected units will not be absolutely simultaneous. Asynchronous switchings leads to a current imbalance at the parallel inverter legs. In the ideal situation switchings would be exactly simultaneous and each leg would take the same amount of the load current. In this paper simulation and measurement results of the parallel connected voltage source inverters (VSI) without intermodule reactors are presented. These results show that a method is needed to synchronize the parallel power converters to get a full use of the parallel system.

Modeling and analysis of the dead-time effects in parallel two-level voltage source inverters

A necessary blanking-time used to prevent a short circuit in the inverter phase leg, finite turn-on and turnoff times of switching devices, and forward voltage drops of switching devices and anti-parallel diodes are known to cause load dependent distortion to inverter output voltages. The objective of this paper is to gain the understanding how the overall effects of the above-mentioned factors affect the circulating current generation between the parallel-connected two-level voltage source inverters. To meet this objective, a circulating current model taking these effects into account is developed. The model, which is an average model in nature, gives an analytical way to consider the significance of these effects to the circulating current generation. To verify the validity of the developed model, the circuit simulation results are shown and compared with the analytical results. The illustrations show that the results obtained with the developed model are in good agreement with the circuit simulations.