Toru Sai

Feedback Loop Analysis and Optimized Compensation Slope of the Current-Mode Buck DC-DC Converter in DCM

Frequency characteristics of the total feedback loop of a current-mode buck DC-DC converter in the discontinuous conduction mode (DCM) are examined by formulating an equivalent small-signal transfer function using a proposed block structure that does not suffer direct influence from the current feedback. Utilizing this transfer function, it is clarified that the type of the compensation slope in a current feedback loop affects the loop frequency characteristics in DCM, and in terms of stability, high voltage gain and large 0-dB frequency bandwidth, the quadratic compensation slope is more effective than the linear compensation slope. The validity of the proposed block structure and formulations and the effectiveness of applying a quadratic compensation slope instead of a linear compensation slope in DCM are verified by comparing calculation results, SPICE simulation results and evaluation results using circuit and measurement data from an MOS current-mode buck DC-DC converter IC that had been previously fabricated. More than 10-dB higher voltage gain, three times larger 0-dB frequency bandwidth, more than 10-degree larger phase margin and faster recovery time in load current change are realizable in DCM compared with the case using a linear compensation slope.

Design of a 1-V operational passive sigma-delta modulator

The 1-V operation of a passive sigma-delta modulator has been realized. The dc voltage in the signal paths in the second-order switched capacitor filter section was set at 0.2 V so that metal-oxide-semiconductor (MOS) switches in the signal paths would have enough gate-to-source voltage to turn on without using a voltage boosting scheme. The input switch was replaced by a passive resistor to avoid floating. By modifying gain coefficients in the feedback and the input paths, the bias voltage of digital-to-analog converter (DAC) can be set to 1 V and 0 V and MOS switches become easily activated. Moreover, the correlated double sampling (CDS) scheme was adopted to suppress the 1/f noise and offset voltage produced at the input of a comparator. Successful operation from 1-V supply voltage was confirmed by circuit simulation using the 0.18-um complementary MOS (CMOS) process.

A method for realizing a fast response time for the output current change of a MOS current-mode buck DC-DC converter which utilizes a quadratic and vin-dependent compensation slope

In this study, a fast response time of less than 10 us has been realized for the sudden output current change between 220 mA and 20 mA of a MOS current-mode buck DC-DC converter which utilizes a quadratic and input-voltage-dependent compensation slope. By using a quadratic and input-voltage-dependent compensation slope, the frequency characteristics of the current feedback loop become constant, and the converters overall frequency characteristics come to be determined by just adjusting the frequency characteristics in the voltage feedback loop. By changing the time constant in an error amplifier to manipulate the phase margin, the converters output voltage change becomes small and its response time becomes fast. The test chip of a MOS current-mode buck DC-DC converter using a 0.35-um CMOS process and a 5 MHz clock realized a 40.8 mV output voltage change and a 7.2 us of the response time.

A 14-bit MOS DAC with current sources free from power-line voltage drop and with output circuits free from code-dependent variable time constant

A 14-bit MOS DAC is described that has current sources that are free from the non-linear current mismatch caused by ground-line voltage drop and output circuits that do not suffer from time-constant change at the output terminal when the input digital code changes. Base current sources are locally classified into two groups with two different values, and the unit current source is constructed by adding one base current source from one group and another base current source from the other group. Eight buffer amplifiers are distributed between the output terminal and current switches to stabilize the voltage at the node where several outputs of unit current sources are tied together and to eliminate the influence of stray capacitances associated with unit current sources and current switches. A 14-bit, 3.3-V DAC was fabricated using 0.35-um CMOS devices. The results show that the DNL and INL are from +0.7 to −0.75 LSB and +1.5 to −1 dB, respectively, and that the SFDR for 2.5-MHz and 10-MHz reconstructed signal waveforms were 77 dB and 67 dB, respectively, with a 50-MHz clock. The current consumption was 25 mA.

A fast and precise circuit simulation method for switching power converters using a mixture of circuits and behavioral models

We propose a fast and precise simulation method for replicating the transient responses and frequency characteristics of switching power converters using a mixture of real circuits and behavioral models. The method used a behavioral simulation tool (Verilog-A), which was supported by an analog simulator such as SPECTRE®. The time-step became variable, however, the nonlinear operation of the circuit was considered and state-space equations were formulated by applying the hybrid-dynamical-system control scheme in behavioral modeling [1]. Each macro block can have either the real schematic and behavioral model. The transient simulation operates in such a way that the analog simulator advances the simulation step by step while obtaining results from behavioral blocks. Further application of the periodic steady state (PSS) and periodic stability (PSTB) analyses, allowed us to obtain the frequency characteristics in short time. For verification, we simulated the circuits of the current-mode buck DC-DC converter IC, which was previously fabricated using a 0.18-um CMOS process. When we chose blocks of a buffer, the switching and output circuits and RS-FF real transistor circuits, while the rest behavioral models, we achieved transient response and frequency characteristics that were 13 and 75 times faster, respectively, than the analog simulator alone, while keeping less than 3.9% and 2.5% of errors compared with ICs evaluation results.