Toshiaki Kurosu

Advanced image placement performance for the current EPL masks

We examined two EPL mask fabrication processes to control precisely image placement (IP) on the EPL masks. One is a wafer process using an electrostatic chuck during an e-beam write and another is a membrane process using a mechanical chuck during the e-beam write. In the wafer process, the global IP is corrected during the e-beam write on the basis of the IP data taken with x-y metrology tool. In the membrane process, the global IP is corrected during the e-beam write on the basis of the data taken with the x-y metrology tool and taken in situ with the e-beam writer. The resist and final global IP (3s) of the wafer process is 7.2 nm and 10.6 nm. For the average local IP errors (3s), the local IP of 5.7 nm at the resist step increases to 14.7 nm at the final step due to process-induced distortions. The local IP could be reduced to 6.0 nm by applying the constant scale value to the mask process. In the membrane process, the resist and final global IP (3s) is 15.3 nm and 17.1 nm. With more detectable alignment marks, it would be possible to improve the global IP. For the average local IP errors (3s) of the membrane process, the average resist and final local IP are 6.7 and 7.1 nm which shows no PID. The two approaches proved to control IP more accurately than the conventional one.

Image placement of large window-size membrane for EPL and LEEPL mask

Large window-size membranes for stencil masks are required to increase the throughput of electron projection lithography (EPL) and low-energy electron projection lithography (LEEPL). In this paper, image placement (IP) accuracy and methodology for correcting stress-induced distortions on 4 X EPL masks are addressed. Although the average of local IP errors (| mean | + 3σ) for reference features across an entire 1mm-window EPL mask is 13.4 nm, the average of errors across an entire 4mm-window EPL mask increases to 20.4 nm, which could be reduced to the required budget with further study on EB writing accuracy or IP corrections. In addition we evaluate local IP errors on 4mm-window mask due to pattern gradients by measuring the placement errors at the edge of dense hole arrays. Applying the correction for stress-induced distortions to EB data, we can reduce the placement errors for dense features to 4.6 nm, which is less than the 10 nm budget allocated for 4mm-window EPL mask at the half-pitch features of 45 nm node. For the global IP, only the measurement repeatability of 7.8 nm contributes to the global IP budget measuring all the global position over an entire 4mm-window EPL mask. And we can meet the required global IP budget. Finally, IP accuracy for a single membrane is also presented, showing the IP error is 24.5 nm (| mean | + 3σ), which compares with that of COSMOS type LEEPL mask. Methodology of measuring the position data on a single membrane, however, remains to be developed.