Toshiki Kizu
Toshiba
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Publication
Featured researches published by Toshiki Kizu.
design, automation, and test in europe | 2009
Takeshi Kodaka; Shunsuke Sasaki; Takahiro Tokuyoshi; Ryuichiro Ohyama; Nobuhiro Nonogaki; Koji Kitayama; Tatsuya Mori; Yasuyuki Ueda; Hideho Arakida; Yuji Okuda; Toshiki Kizu; Yoshiro Tsuboi; Nobu Matsumoto
In this paper, we propose a scalable and transparent parallelization scheme using threads for multi-core processor. The performance achieved by our scheme is scalable to the number of cores, and the application program is not affected by the actual number of cores. For the performance efficiency, we designed the threads so that they do not suspend and that they do not start their execution until the data necessary for them are available. We implemented our design using three modules: the dependency controller, which controls dependencies among threads, the thread pool, which manages the ready threads, and the thread dispatcher, which fetches threads from the pool and executes them on the core. Our design and implementation provide efficient thread scheduling with low overhead. Moreover, by hiding the actual number of cores, it realizes transparency. We confirmed the transparency and scalability of our scheme by applying it to the H.264 decoder program. With this scheme, modification of application program is not necessary even if the number of cores changes due to disparate requirements. This feature makes the developing time shorter and contributes to the reduction of the developing cost.
design, automation, and test in europe | 2013
Takeshi Kodaka; Akira Takeda; Shunsuke Sasaki; Akira Yokosawa; Toshiki Kizu; Takahiro Tokuyoshi; Hui Xu; Toru Sano; Hiroyuki Usui; Jun Tanabe; Takashi Miyamori; Nobu Matsumoto
We developed a method that predicts the required number of cores for executing threads in the near future on a many-core processor. It is designed for low power consumption without performance degradation. The evaluation result confirmed the proposed method is effective on a 32-cores processor.
2015 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XVIII) | 2015
Akira Takeda; Akira Yokosawa; Shintaro Sano; Shunsuke Sasaki; Takeshi Kodaka; Takahiro Tokuyoshi; Toshiki Kizu
On wearable devices where an MCU primarily remains in an idle state, keeping the MCU in a deep sleep mode during idle periods can lead to significant power reduction. Since the deep sleep mode has a relatively high wake-up overhead, one of the effective techniques for power reduction is to decrease the wake-up frequency of the MCU. Meanwhile, due to the recent trend of increasing the number of sensors embedded in wearable devices, the MCU must wake up more frequently for data acquisitions from the sensors. This indicates an increase in power consumption caused by frequent wakeups. In this paper, we propose a new method to achieve power reduction of the MCU for wearable applications. The applications acquire data periodically from multiple sensors. Our proposed method achieves low power consumption by gathering the scattered data acquisitions of the sensors and decreasing the wake-up frequency. The experimental result shows that the proposed method achieved an 8.5-31% power reduction in the MCU.
Archive | 1996
Tatsunori Kanai; Seiji Maeda; Toshiki Kizu; Hiroshi Yao
Archive | 1997
Toshio Shirakihara; Tatsunori Kanai; Toshiki Kizu
Archive | 2000
Tatsunori Kanai; Toshiki Kizu; Seiji Maeda; Takeshi Yokokawa; Hiroshi Yao; Osamu Torii; Hirokuni Yano; Hisako Tanaka
Archive | 1996
Hiroshi Toshiba-Shinkoyasu-Daiichi-ryo Yao; Tatsunori Kanai; Toshiki Kizu; Seiji Maeda
Archive | 2000
Tatsunori Kanai; Osamu Torii; Toshiki Kizu; Seiji Maeda; Hiroshi Yao; Hirokuni Yano
Archive | 2009
Yuji Ishikawa; Toshiki Kizu; Ryuichiro Ohyama
Archive | 2004
Tatsunori Kanai; Hirokuni Yano; Toshiki Kizu; Hiroshi Yao; Seiji Maeda; Osamu Torii