Toshitsugu Yuba

An Architecture Of A Dataflow Single Chip Processor

<italic>A highly parallel (more than a thousand) dataflow machine</italic> EM-4 <italic>is now under development. The</italic> EM-4 <italic>design principle is to construct a high performance computer using a compact architecture by overcoming several defects of dataflow machines. Constructing the</italic> EM-4, <italic>it is essential to fabricate a processing element (PE) on a single chip for reducing operation speed, system size, design complexity and cost. In the</italic> EM-4, <italic>the PE , called</italic> EMC-R, <italic>has been specially designed using a 50,000-gate gate array chip. This paper focuses on an architecture of the</italic> EMC-R. <italic>The distinctive features of it are: a strongly connected arc dataflow model; a direct matching scheme; a RISC-based design; a deadlock-free on-chip packet switch; and an integration of a packet-based circular pipeline and a register-based advanced control pipeline. These features are intensively examined, and the instruction set architecture and the configuration architecture which exploit them are described.</italic>

A performance evaluation of a Lisp-based data-driven machine (EM-3)

In this paper, a Lisp-based data-driven machine with a novel parallel control mechanism and its performance evaluation are presented. The proposed control mechanism is the natural extension of a data-driven scheme to function evaluation and is achieved by packet communication architecture. First, the organization of the data-driven machine is described and, then the results of the simulation studies are shown which confirm the effectiveness of the control mechanism. The performance characteristics of the data-driven machine obtained by the software simulator are also given.

Dataflow computing models, languages, and machines for intelligence computations

The authors compare dataflow computing models, languages, and dataflow computing machines for numerical and nonnumerical computations. The high-level-language-graph transformations that must be performed to achieve high performance for numerical and nonnumerical programs executed in a dataflow computing environment are described for Lisp, using the DCBL transformations. Some general problems of dataflow computing machines are discussed. Performance evaluation measurements obtained by executing benchmark programs in the ETL nonnumerical dataflow computing environment, the EM-3, are presented. >

SIGMA-1: A dataflow computer for scientific computations

Abstract This paper presents an overview of the SIGMA-1, a large-scale dataflow computer being developed at the Electrotechnical Laboratory, Japan. The SIGMA-1 is designed to accommodate about two hundred dataflow processing elements. Its estimated average speed is one hundred MFLOPS for certain numerical computations. Various aspects of the SIGMA-1, such as the organization of a processing element, the matching memory unit, the structure memory and the communication network, are described. The present status and development plans of the SIGMA-1 project are detailed. It is predicted that the SIGMA-1 will give higher speed over a wide range of applications than conventional von Neumann computers.

Dataflow computer development in Japan

This paper describes the research activity on dataflow computing in Japan focusing on dataflow computer development at the Electrotechnical Laboratory (ETL). First, the history of dataflow computer development in Japan is outlined. Some distinguished milestones in the history are mentioned in detail. Second, two types of dataflow computing systems developed at ETL, SIGMA-1 and EM-4, are described with their research goals. The fundamental characteristics of the both systems are given and some comparisons are made. Finally, future problems toward new generation computer systems to meet the challenge of Tera FLOPS machines are discussed.

Binary search networks: a new method for key searching

Abstract A novel method for key searching, binary search networks, is proposed, and its search, insertion, and deletion algorithms are presented. A binary search network is an extension of a binary search tree which is widely used as a practical key search method. Some properties of binary search networks are discussed, and the optimization problem of minimizing a search cost is remarked upon. The advantages and disadvantages of binary search networks relative to binary search trees are also discussed.

The Gene Concept and its Implementation for a Dataflow Schemed Parallel Computer

A dataflow scheme is suitable for multi-processor systems to extract parallelism naturally, but mapping ideal parallel computations to limited execution resources is a major problem. The Gene concept is proposed to provide flexible control of parallelism in dataflow schemed parallel computers. A gene is the property carried by data and propagated from ancestor operations to descendant operations. In this way, the Gene groups the operations according to properties. By checking the properties, the Gene can cease and suspend the execution of operation groups, and control the priority of execution among groups. These functions are essential for general purpose highly parallel computers allowing multi-programming, multi-user and standalone usage. This paper proposes the Gene concept and discusses its implementation and usage, then shows its effectiveness by simulations.