Toshiya Kotani

Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control

Although Self-Aligned Double and Quadruple Patterning (SADP, SAQP) have become the most promising processes for sub-20 nm and sub-14 nm node advanced technologies, not all wafer images are realized by them. In advanced technologies, feasible wafer images should be generated effectively by utilizing SADP and SAQP where a wafer image is uniquely determined by a selected mandrel pattern. However, predicting the wafer image of a mandrel pattern is not easy. In this paper, we propose a routing method of generating a feasible wafer image satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SADP) or three colors (SAQP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, hotspot reduction by dummy pattern flipping is proposed. In experiments, feasible wafer images meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Automated hot-spot fixing system applied for metal layers of 65 nm logic devices

Hot spot clearance using process simulation is indispensable under low-k1 lithography process for logic devices of 65 nm and below. Hot spots such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Appropriate calibration of design rule (DR), mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of design at hot spot will be effective, but it takes too much time to determine how to modify layout to be consistent with DR, MDP/OPC rule, and the process often needs to be iterative. Therefore, there is a need for an automated hot spot fixing system is capable of fixing design layout so as to avoid fatal hot spot occurrence, with sufficient process margin and short turn around time (TAT). We developed an automated hot-spot fixing system, Hot Spot Fixer (HSF). The basic system flow in the developed system is as follows; Design data is processed with the conventional mask data preparation process. Then, process simulation is performed to extract hot spots. The hot spots are categorized by lithography error mode, critical level, and surrounding context. An intelligent hot-spot modification instructor, taking the surrounding situation into consideration, generates modification guide for the every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. If necessary, several modification candidates are indicated and the user can choose the most adequate one from them. The design modification process is verified from every aspect, using Design Rule Checker (DRC) and process simulation. The modified design data, with reduced potential hot spot compared with pre-modification design, is processed under the conventional mask data preparation process again, and then makes mask data, which will reduce the number of potential hot spot. We applied the HSF system to metal layer of logic devices of 65 nm and then the hot spots are almost diminished throughout a full chip within twelve hours. Thus HSF feasibility has been proved for metal layers in 65 nm node and below with full chip data volume.

Lithography oriented DfM for 65 nm and beyond

As Technology node is advancing, we are forced to use relatively low resolution lithography tool. And these situation results in degradation of pattern fidelity. hot spot, lithographic margin-less spot, appears frequently by conventional design rule methodology. We propose two design rule methodology to manage hot spot appearances in the stage of physical pattern determination. One is restricted design rule, under which pattern variation is very limited, so hot spot generation can be fully controlled. Second is complex design rule combined with lithography compliance check (LCC) and hot spot fixing (HSF). Design rule, by itself, has a limited ability to reduce hot spot generation. To compensate the limited ability, both LCC including optical proximity correction and process simulation for detecting hot spots and HSF for fixing the detected hot spots are required. Implementing those methodology into design environment, hot spot management can be done by early stage of physical pattern determination. Also newly developed tool is introduced to help designers easily fixing hot spots. By using this tool, the system of automatic LCC and HSF has been constructed. hot spots-less physical patterns through this system can be easily obtained and turn-back from manufacture to design can be avoided.

Process window aware layout optimization using hot spot fixing system

The feasibility of Hot Spot Fixing (HSF) system in DfM flow is studied and reported. Hot spot fixing using process simulation is indispensable under low-k1 lithography process for logic devices with advanced design rule (DR). Hot spot such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Proper calibration of DR, mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with most careful calibration of every process, unexpected potential hot spots are occasionally left in the design layout 1-2. OPC optimization is useful for maximizing common process margin, but it cannot expand individual patterns process margin without modification of design layout. So, at an early design stage, hot spot extraction using lithography compliance check (LCC) and manual modification of design at hot spots will be a simple and useful method. The problem is that, it is difficult to determine how to modify layout in order to be consistent with DR, MDP/OPC rule. For proper layout modification, intimate knowledge of the entire process would be necessary, and moreover, the modification work often tends to be iterative, and thus time-consuming. Therefore, using our automated HSF system in the cell design stage and also the chip design stage is helpful for fixing design layout while avoiding fatal hot spot occurrence, with enough process margin and also with short turnaround time (TAT) 3-4. The basic system flow in the developed system is as follows; LCC extracts potential hot spots, and the hot spots are categorized by lithography error mode, grade, and surrounding context. And then, hot spot modification instructor, taking the surrounding situation into consideration, generates modification guide for every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. The design modification process is verified with design-rule checker (DRC) and process simulation to confirm hot spot elimination without side effect. In this work, HSF is implemented in the design flow for various logic devices of 65 nm node. We extend modification target layers to multiple critical layers, including active area, poly, local metal wire and intermediate metal wire. The feasibility of the provided HSF system has been studied by applying it to around one hundred data of various sizes with respect to pattern fixing rate and turn around time (TAT). Moreover, process margin expansion including depth of focus (DOF) and exposure latitude (EL), in small layout was verified using process simulation and also by experimental results, namely, scanning electron microscope (SEM) images of focus exposure matrix. The detailed results are shown in the paper.

Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods

Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed.

Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints

In this paper, we propose a new flexible routing method for Self-Aligned Double Patterning (SADP). SADP is one of the most promising candidates for patterning sub-20 nm node advanced technology but wafer images must satisfy tighter constraints than litho-etch-litho-etch process. Previous SADP routing methods require strict constraints induced from the relation between mandrel and trim patterns, so design freedom is unexpectedly lost. Also these methods assume to form narrow patterns by trimming process without consideration of resolution limit of optical lithography. The proposed method realizes flexible SADP routing with dynamic coloring requiring no decomposition to extract mandrel patterns and no worries about coloring conflicts. The proposed method uses realizable trimming process only for insulation of patterns. The effectiveness of the proposed method is confirmed in the experimental comparisons.

Yield-enhanced layout generation by new design for manufacturability (DfM) flow

Design for manufacturability ( DfM ) flow consisting of a new lithography design approach at the design rule definition stage and manufacturability check at physical layout stage is proposed to clean up hot spots and guarantee the final layouts to be free of hot spots under low-k1 lithography condition. At the initial development stage, design rules ( DRs ), resolution enhancement technique ( RET ) and optical proximity correction ( OPC ) methods and critical dimension ( CD ) target and specification are determined by the new lithography design approach to reduce hot spots next-generation’s tentative layout made by the compactor. At the physical layout stage, a manufacturability check ( MC ) is essential to wipe out hot spots resulted from immaturity of DRs and process parameters fixed at the initial development stage by making three feedback approaches: the refinement of design rule, the repair of hot spots by designers and the refinement of OPC parameters and/or methods. Also, an alternative of layout modification or OPC improvement for cleaning hot spots are cleared by categorization of CD variation induced by some dose and focus conditions and an error of CD average for the target pattern. The proposed DfM flow is found to be highly effective for the robust pattern formation under the low-k1 lithography condition.

Hierarchical optical proximity correction on contact hole layers

As the size of contact holes shrinks below 0.2 /spl mu/m, optical proximity correction (OPC) on contact hole layers becomes essential. When correcting contact holes, 1-dimensional correction is not applicable, and 2-dimensional correction is required, which needs much more intensive computation. To reduce computation, it is very effective to take advantage of the hierarchy of the input data. In order to further accelerate the OPC calculation, we adopted pattern matching into the OPC system, which can extract the hierarchy implicit in the layout data.

Self-aligned quadruple patterning-aware routing

Self-Aligned Quadruple Patterning (SAQP) is one of the most leading techniques in 14 nm node and beyond. However, the construction of feasible layout configurations must follow stricter constraints than in LELELE triple patterning process. Some SAQP layout decomposition methods were recently proposed. However, due to strict constraints required for feasible SAQP layout, the decomposition strategy considering an arbitrary layout does not seem realistic. In this paper, we propose a new routing method for feasible SAQP layout requiring no decomposition. Our method performs detailed routing by correct-by-construction approach and offers compliant layout configuration without any pitch conflict.

Automated hot-spot fixing system applied to the metal layers of 65-nm logic devices

Hot-spot clearance using process simulation is indispensable for low-k 1 lithography processes. Hot spots will occur mainly depending on local pattern context. Appropriate calibration of design rules, mask data preparation, resolution enhancement techniques, and optical proximity effect correction will reduce potential hot spots. However, pattern layout variety is so enormous that, even with the most careful calibration of every process, an unexpected potential hot spot is occasionally left in the design layout. Manual modification of the design at the hot spot will be effective, but it takes too much time. Therefore, there is a need for an automated hot-spot fixing system so as to avoid fatal hot-spot occurrence, with sufficient process margins and short turnaround time. We developed an automated hot-spot fixing system, the hot-spot fixer (HSF). Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. We applied the HSF system to the metal layer of logic devices of 65 nm and most of the hot spots were diminished throughout a full chip within 12 hours. Thus, HSF feasibility has been proved for metal layers in the 65-nm node and below with full-chip data volume.