Toshiya Uozumi

A digital PLL with two-step closed-locking for multi-mode/multi-band SAW-less transmitter

This paper presents a digital phase locked loop (DPLL) with two-step closed-locking technique. The two-step locking allows us to use a simple phase detector, which achieves wide phase detect range and has no complex circuits for glitch compensation. The DPLL has three digital controlled oscillators (DCO) for multi-mode/multi-band operation. The DPLL covers GSM quad-band, and several bands of WCDMA / LTE. The DPLL improves a close-in noise by 17 dB compared with the conventional count-assisted locking, which causes glitch error substantially. The phase error is less than 3.0 degrees in all bands for various conditions. The faraway phase noise is -165dBc/Hz at 20MHz, -161dBc/Hz at 190MHz, and -158dBc/Hz at 120MHz in each TX output, respectively.

A Δ∑-modulator-less digitally-controlled oscillator using fractional capacitors for GSM/EDGE transmitter

A ΔΣ-modulator (DSM)-less digitally controlled oscillator (DCO) based on 65-nm CMOS technology, incorporating a fractional-capacitor and ground-shield techniques, for a GSM/EDGE transmitter was developed. The fractional-capacitor and ground-shield techniques, respectively, achieve high frequency resolution (0.6 kHz) without a conventional DSM and small differential non linearity (DNL) of DCO gains (0.12 LSB). A transmitter using the DCO exhibits both low phase error (0.9°) and in-specification receiver-band noise (<;-165 dBc/Hz) thanks to the high frequency resolution and small DNL.

A 43%-efficiency 20dBm sub-GHz transmitter employing rise-edge-synchronized harmonic calibration with 33.3% duty cycle

A high efficiency class-E power amplifier (PA) is proposed with only 3 external components. The PA is driven by a 33.3% duty cycle with a rise-edge-synchronized harmonic calibration. The 33.3% duty cycle operation lowers the drain voltage swing as well as the 3rd harmonics, and the calibration optimizes the duty imbalance and the phase difference between the differential signals, improving the PA efficiency and eliminating the external harmonic filters. The PA fabricated in 40nm CMOS has achieved the output power of 20dBm and the TX efficiency of 43% with “only 3 external components” in the impedance matching network.