Toshiyuki Hama

Curvilinear detailed routing algorithm and its extension to wire-spreading and wire-fattening

This article describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gaos algorithm by resolving its bottleneck related to generation of fan-shaped forbidden regions along a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through which wires can pass. From the experiments we obtained the result that the average CPU time of the detailed routing algorithm is almost linear to the length of a wire. Since the curvilinear detailed routing is efficient in terms of space usage, the proposed algorithm is important especially for densely wired printed circuit boards such as PGA packages, BGA packages, and MCMs. We can also expect improvements on the electrical characteristics and the production yield by applying wire-spreading and wire-fattening to them.

Curvilinear detailed routing with simultaneous wire-spreading and wire-fattening

This paper describes an algorithm for curvilinear detailed routing. We significantly improved the average time performance of Gaos algorithm by resolving its bottleneck related to generation of fan-shaped forbidden regions along a wire. We also describe a method for simultaneous wire-spreading and wire-fattening, which consists of enlarging forbidden regions generated by the detailed routing algorithm as long as there remains any space through which wires can pass. From the experiments we obtained the result that the average CPU time of the detailed routing algorithm is almost linear to the length of a wire. Since the curvilinear detailed routing is efficient in terms of space usage, the proposed algorithm is important especially for densely wired printed circuit boards such as pin grid array packages, ball grid array packages, and multichip modules. We can also expect improvements on the electrical characteristics and the production yield by applying wire-spreading and wire-fattening to them.

Topological routing path search algorithm with incremental routability test

The article describes a topological routing path search algorithm embedded in the auto-router for printed circuit boards. The algorithm searches for a topological path that is guaranteed to be transformable into a physical wire satisfying design rules. The authors propose a method for incrementally verifying design rules during topological path search in a graph based on constrained Delaunay triangulation, and describe several improvements to the routing path search algorithm that remedy the overhead of the routability test and avoid combinatorial explosion.