Toshiyuki Miyauchi

High-performance programmable SISO decoder VLSI implementation for decoding turbo codes

We developed a high-performance programmable SISO decoder LSI for decoding turbo codes based on the SW-log-BCJR algorithm. This LSI is based on the original architecture and memory management method, which guarantees the order of the soft-output to be the same as soft-input without attaching LIFO memory. Moreover, we propose new accurate implementation on 4-input log-sum operations used in the recursion of /spl alpha/ and /spl beta/ for codes of rate 2/3 and 3/3. This technique enables high operating frequency and low coding loss simultaneously. The interleaver and inevitable delay lines required to realize the turbo decoders are embedded on the chip so the most turbo code applications, including parallel concatenated convolutional codes (PCCC), serial concatenated convolutional codes (SCCC), turbo trellis coded modulation (TTCM) and serial concatenated trellis coded modulation (SCTCM), can easily be implemented scalably by cascading this LSI. The LSI is fully programmable for code types, code polynomials and interleaver patterns and applicable for BPSK, QPSK and 8-PSK with arbitrary signal constellation. An operating frequency of 100 MHz is achieved using CMOS 0.25 /spl mu/m process whereas the coding loss according to implementation is kept within 0.03 dB.

Soft-Output Decoding of 17 Parity Preserve/Prohibit Repeated Minimum Transition Runlength (PP) Code

We propose a novel trellis decoding technique for soft-output decoding of 17 parity preserve/prohibit repeated minimum transition runlength (PP) code. The trellis of the 17 PP code has 21 states and 79 branches. We applied the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to the trellis to obtain a soft-input soft-output (SISO) decoder. Using this SISO decoder, we have developed a turbo-coded 17 PP system for optical recording. It is experimentally confirmed that the turbo-coded 17 PP system effectively improves the bit error rate (BER) of high-density optical storage.

Hardware implementation of soft-decision decoding for Reed-Solomon code

We implemented a soft-decision decoder of (204,188)-Reed-Solomon code, which is used widely in standards for satellite, terrestrial, and other broadcasting systems. The decoder employs a list decoding technique using iterative adaptive belief propagation and bounded distance decoding. One decoded word is chosen from the list by MAP decoding, and some ideas are applied to reduce its complexity. When the channel throughput is 32 Mbps, the decoder works at 88 MHz in an FPGA, and obtains 1 dB performance gain compared with ordinary hard-decision decoders.

Application of Low Density Parity Check Codes to High-Density Optical Disc Storage Using 17PP Code

We are developing a high-density recording method for optical disc storage. To improve the density of optical recording systems and increase the operational margin, we previously optimized the PR17PP trellis by merging the PR(1221) trellis and we achieved a higher recording density in optical disc storage. In this paper, we propose a new high-density low density parity check (LDPC)-coded PR17PP system with PR(12221)-ML. We experimentally confirmed that the system significantly increases the tilt margin of 36.0 GB optical disc with Blu-ray disc parameters.

A High Performance and Programmable Decoder VLSI for Structured LDPC Codes

We have developed a high performance and programmable LDPC decoder VLSI for decoding structured LDPC codes. In this paper, the architecture of the decoder and the structured parity check matrices are described along with the quantization method. We adopt floating point (FP) quantization method in check node processors so as to shrink down the complexity of look up tables (LUTs) of the Gallager function, and avoid performance degradation. Finally, simulation results show that the FP quantization method achieves high performance for wide range of code rates

An optimization method for designing high rate and high performance SCTCM systems with in-line interleavers

We present a method for designing high-rate, high-performance SCTCM (serially concatenated trellis coded modulation) systems with in-line interleavers. Using in-line EXIT charts and ML performance analysis, we develop criteria for choosing constituent codes and optimization methods for selecting the best ones. To illustrate our methods, we show that an optimized SCTCM system with an in-line interleaver for rate r = 5/6 and 64QAM has better performance than other turbo-like TCMs with the same parameters.