Tosiron Adegbija

Analysis of cache tuner architectural layouts for multicore embedded systems

Due to the memory hierarchys large contribution to a microprocessors total power, cache tuning is an ideal method for optimizing overall power consumption in embedded systems. Since most embedded systems are power and area constrained, the hardware and/or software that orchestrate cache tuning - the cache tuner - must not impose significant power and area overhead. Furthermore, as embedded systems increasingly trend towards multicore, inter-core data sharing, communication, and synchronization impose additional cache tuner design complexity, necessitating cross-core cache tuning coordination. In order to minimize cache tuner overhead, cache tuner design must consider these overheads and scalability. Whereas prior work proposes low-overhead cache tuners, scalability to multicore systems requires additional considerations. In this work, we present a low-overhead, scalable cache tuner and extensively evaluate various cache tuner design tradeoffs with respect to power and area for constrained multicore embedded systems. Based on our analysis, we formulate valuable insights and designer-assisted guidelines for modeling scalable and efficient cache tuners that best achieve optimization goals while maintaining power and area constraints.

Microprocessor Optimizations for the Internet of Things: A Survey

The Internet of Things (IoT) refers to a pervasive presence of interconnected and uniquely identifiable physical devices. These devices’ goal is to gather data and drive actions in order to improve productivity, and ultimately reduce or eliminate reliance on human intervention for data acquisition, interpretation, and use. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumption and latency. Edge computing reduces these costs by performing computations at the edge nodes, prior to data transmission, to interpret and/or utilize the data. While much research has focused on the IoT’s connected nature and communication challenges, the challenges of IoT embedded computing with respect to device microprocessors has received much less attention. This paper explores IoT applications’ execution characteristics from a microarchitectural perspective and the microarchitectural characteristics that will enable efficient and effective edge computing. To tractably represent a wide variety of next-generation IoT applications, we present a broad IoT application classification methodology based on application functions, to enable quicker workload characterizations for IoT microprocessors. We then survey and discuss potential microarchitectural optimizations and computing paradigms that will enable the design of right-provisioned microprocessors that are efficient, configurable, extensible, and scalable. This paper provides a foundation for the analysis and design of a diverse set of microprocessor architectures for next-generation IoT devices.

Phase-based Cache Locking for Embedded Systems

Since caches are commonly used in embedded systems, which typically have stringent design constraints imposed by physical size, battery capacity, real-time deadlines, etc., much research focuses on cache optimizations, such as improved performance and/or reduced energy consumption. Cache locking is a popular cache optimization that loads and retains/locks selected memory contents from an executing application into the cache to increase the caches predictability. Previous work has shown that cache locking also has the potential to improve cache performance and energy consumption. In this paper, we introduce phase-based cache locking, which leverages an applications varying runtime characteristics to dynamically select the locked memory contents to optimize cache performance and energy consumption. Experimental results show that our phase-based cache locking methodology can improve the data caches miss rates and energy consumption by an average of 24% and 20%, respectively.

Enabling Right-Provisioned Microprocessor Architectures for the Internet of Things

The Internet of Things (IoT) consists of embedded low-power devices that collect and transmit data to centralized head nodes that process and analyze the data, and drive actions. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumed and latency. Edge computing performs computations at the edge nodes prior to data transmission to interpret and/or utilize the data, thus reducing transmission costs. In this work, we seek to understand the interactions between IoT applications’ execution characteristics (e.g., compute/memory intensity, cache miss rates, etc.) and the edge nodes’ microarchitectural characteristics (e.g., clock frequency, memory capacity, etc.) for efficient and effective edge computing. Thus, we present a broad and tractable IoT application classification methodology and using this classification, we analyze the microarchitectural characteristics of a wide range of state-of-the-art embedded system microprocessors and evaluate the microprocessors’ applicability to IoT computation using various evaluation metrics. We also investigate and quantify the impact of leakage power reduction on the overall energy consumption across different architectures. Our work provides insights into the microarchitectural characteristics’ impact on system performance and efficiency for various IoT application requirements. Our work also provides a foundation for the analysis and design of a diverse set of microprocessor architectures for IoT edge computing.Copyright

Energy-efficient phase-based cache tuning for multimedia applications in embedded systems

The proliferation of multimedia applications in embedded systems has led to a research focus on optimizing the energy consumption of these applications without significantly degrading the execution time and adhering to data processing deadline constraints. To maximize optimization potential, phase-based tuning methodologies specialize system configurations to different phases of application execution with respect to design constraints. Multimedia applications are ideal candidates for phase-based tuning since these applications exhibit variable execution characteristics. In this paper, we propose a phase-based tuning methodology for multimedia applications that leverages application characteristics to determine the best cache configurations for different phases of execution. Results reveal that phase-based tuning for multimedia applications determines cache configurations within 1% of the optimal on average and yields an average energy delay product savings of 29%.

Dynamic phase-based tuning for embedded systems using phase distance mapping

Phase-based tuning specializes a systems tunable parameters to the varying runtime requirements of an applications different phases of execution to meet optimization goals. Since the design space for tunable systems can be very large, one of the major challenges in phase-based tuning is determining the best configuration for each phase without incurring significant tuning overhead (e.g., energy and/or performance) during design space exploration. In this paper, we propose phase distance mapping, which directly determines the best configuration for a phase, thereby eliminating design space exploration. Phase distance mapping applies the correlation between a known phases characteristics and best configuration to determine a new phases best configuration based on the new phases characteristics. Experimental results verify that our phase distance mapping approach determines configurations within 3% of the optimal configurations on average and yields an energy delay product savings of 26% on average.

Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems

Phase-based tuning increases optimization potential by configuring system parameters for application execution phases. Previous work proposed phase distance mapping (PDM), which relied on extensive a priori analysis of executing applications to dynamically estimate the best configuration using the correlation between phases. We propose DynaPDM, a new dynamic phase distance mapping methodology that eliminates a priori designer effort, dynamically analyzes phases, and determines the best configurations, yielding average energy delay product savings of 28%-an 8% improvement on PDM-and configurations within 1% of the optimal.

Exploiting Configurability as a Defense against Cache Side Channel Attacks

Caches have significant impact on an embedded systems performance and energy consumption. As a result, much prior research has focused on cache optimizations to minimize energy consumption and improve performance. Caches are also highly susceptible to side channel attacks, wherein an attacker analyzes leaked information from side channels to extract private information. A key challenge of security mechanisms is that they incur overheads, which can potentially impede optimization goals. Since configurability has been widely studied as a viable and effective cache optimization, we explore using configurability as a moving target defense against cache side channel attacks, while minimizing the attendant overheads of designing secure caches. We present experimental results to show that using configurability as a defense mechanism is very promising, and present future research directions towards enabling secure caches through configurability.

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems

Non-volatile memory (NVM) technologies have recently emerged as alternatives to traditional SRAM-based cache memories, since NVMs offer advantages such as non-volatility, low leakage power, fast read speed, and high density. However, NVMs also have disadvantages, such as high write latency and energy, which necessitate further research into robust optimization techniques. In this paper, we propose and evaluate configurable non-volatile memories (configNVM) as a viable NVM optimization technique, and show that configNVMs can reduce the caches energy consumption by up to 60%, with minimal performance degradation. We describe the knowledge gaps that must be filled to enable configNVMs, and show that configNVMs offer new opportunities for energy efficient caching in embedded systems.

TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems

Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system’s temperature not only affects the system’s reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead.