Tracy C. Denk

Architectures for lattice structure based orthonormal discrete wavelet transforms

This paper presents efficient single-rate architectures for the orthonormal discrete wavelet transform (DWT). Folded and digit-serial architectures are derived from an efficient lattice implementation of two-channel FIR paraunitary systems known as the quadrature mirror filter (QMF) lattice. Folded architectures are derived by applying systematic folding techniques to multirate systems. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The number of multipliers and adders required for both the folded and digit-serial lattice-based architectures approaches one-half the number required to implement similar systems based on direct-form filter implementations as the order of the FIR filters becomes large. This makes folded and digit-serial QMF lattice structures attractive choices for applications of the orthonormal DWT which require low area and low power dissipation.<<ETX>>

VLSI architectures for lattice structure based orthonormal discrete wavelet transforms

We present efficient single-rate architectures for the one-dimensional orthonormal discrete wavelet transform (DWT). In the paper we make two contributions. First, we show that architectures that are based on the quadrature mirror filter (QMF) lattice structure require approximately half the number of multipliers and adders than corresponding direct-form structures. Second, we present techniques for mapping the 1-D orthonormal DWT to folded and digit-serial architectures which are based on the QMF lattice structure. For folded architectures, we discuss two techniques for mapping the QMF lattice structure to hardware. For digit-serial architectures, we show that any two-channel subband system can be implemented using digit-serial processing techniques by utilizing the polyphase decomposition. Using this result, we describe an orthonormal DWT architecture which uses the QMF lattice structure and digit-serial processing techniques. The proposed folded and digit-serial QMF lattice structures are attractive choices for implementations of the orthonormal DWT which require low area and low power dissipation.

Calculation of minimum number of registers in 2-D discrete wavelet transforms using lapped block processing

This paper considers architecture design of lapped block processing based discrete wavelet transforms. The emphasis is on computing the minimum number of registers required for various data format converters. Using life-time analysis, it is shown that the total number of on-chip line delays required for this architecture is approximately (N-1) where N is the order of the FIR filters used for the computation of the discrete wavelet transform.<<ETX>>

Synthesis of folded pipelined architectures for multirate DSP algorithms

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms.

Exhaustive scheduling and retiming of digital signal processing systems

Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signal processing algorithms. In this paper, techniques are developed for generating all scheduling and retiming solutions for a strongly connected data-flow graph, allowing a designer to explore the space of possible implementations. Formulations are developed for two scheduling problems. The first scheduling problem assumes a bit-parallel target architecture. The formulation for this problem is general because it considers retiming the data-flow graph as part of scheduling, and this formulation reduces to the retiming formulation as a special case. The second scheduling problem assumes a bit-serial target architecture. Based on these formulations, the conditions for a legal scheduling solution are derived, and a systematic technique is presented for exhaustively generating all legal scheduling solutions for a strongly connected data-flow graph. Since retiming is a special case of scheduling, this systematic technique can also be used for exhaustively generating all legal retiming solutions. A technique is also developed for exhaustively generating only those bit-parallel schedules which satisfy a given set of resource constraints. The techniques for exhaustively generating scheduling and retiming solutions are demonstrated for several filters. For example, we show that a simple filter such as the biquad has 224 possible retiming solutions for a latency of one time unit. We also show that a fifth-order wave digital elliptic filter has 4.7 million and 580 million scheduling solutions for iteration periods of 17 and 18, respectively.

Combining neural networks and the wavelet transform for image compression

The authors present a new image compression scheme which uses the wavelet transform and neural networks. Image compression is performed in three steps. First, the image is decomposed at different scales, using the wavelet transform, to obtain an orthogonal wavelet representation of the image. Second, the wavelet coefficients are divided into vectors, which are projected onto a subspace using a neural network. The number of coefficients required to represent the vector in the subspace is less than the number of coefficients required to represent the original vector, resulting in data compression. Finally, the coefficients which project the vectors of wavelet coefficients onto the subspace are quantized and entropy coded. The advantages of various quantization schemes are discussed. Using these techniques, a 32 to 1 compression at peak SNR of 29 dB was obtained.<<ETX>>

Systolic VLSI architectures for 1-D discrete wavelet transforms

This paper presents systolic VLSI architectures for the discrete wavelet transform (DWT) and inverse discrete wavelet transform (IDWT) which operate on one-dimensional signals. Previously, a dependence graph (DG) of the DWT has been presented which enables systolic mapping techniques to be used to derive DWT architectures. We use this DG to systematically derive new DWT architectures. In addition, we present a DG for the IDWT and use it to systematically derive new IDWT architectures. The resulting DWT and IDWT architectures are scalable with filter length and number of octaves, modular, have high hardware utilization, and use fixed-coefficient multipliers. These properties make them well-suited for VLSI implementation.

Reconfigurable hardware for efficient implementation of programmable FIR filters

We present the architecture of a programmable FIR filter for use in DSP and communication applications. A filter with this architecture is capable of running a wide variety of single-rate and multirate filtering algorithms with low latency. Flexibility is achieved by distributed register files that store input data and filter coefficients. The functionality of the filter is programmed by a set of pipelined control signals that are independent of the filter length. We demonstrate how to generate these control signals for a variety of configurations. In addition to its flexibility, the architecture is scalable, modular, and has no broadcast signals, making it ideally suited for VLSI implementations.

Lower bounds on memory requirements for statically scheduled DSP programs

This paper presents novel techniques for computing the minimum number of memory locations in statically scheduled digital signal processing (DSP) programs. Two related problems are considered. In the first problem, we compute the minimum number of memory locations required for a scheduled program assuming that no circuit transformations (such as pipelining and retiming) are to be performed after scheduling. For this problem, we consider memory minimization for theoperation-constrained, processor-constrained andunconstrained memory models which represent various restrictions on how data can be allocated to memory. Then we consider the second problem, where memory minimization for a scheduled program is considered simultaneously with retiming using a variation of the retiming problem referred to as theminimum physical storage location (MPSL) retiming. While both problems consider memory minimization for scheduled programs, the second problem minimizes memory using retiming whereas the first problem performs no retiming. The scheduling results obtained from the MARS design system are used to compare memory requirements in the context of both of these problems. Our experiments show that MARS performs an optimal retiming for the schedule it generates. These memory requirements are then compared with an integer linear programming solution to the scheduling problem which is optimal under the unconstrained memory model. It is concluded that the schedule obtained by the MARS system achieves optimality or near-optimality with respect to register minimization.

Two-dimensional retiming with low memory requirements

This paper considers throughput and memory requirements in architectures which operate on two-dimensional (2D) digital signals. We present a novel technique for retiming a 2D data-flow graph to meet a given throughput constraint while keeping the memory required by the architecture low. This technique, which we call orthogonal two-dimensional retiming, is posed as two linear programming problems which can be solved in polynomial time. Our results show that, for a given throughput constraint, the orthogonal two-dimensional retiming formulation leads to architectures which require less memory than architectures designed using previously known techniques.