Trang Hoang

A robust algorithm for detection and classification of traffic signs in video data

The accurate identification and recognition of the traffic signs is a challenging problem as the developed systems have to address a large number of imaging problems such as motion artifacts, various weather conditions, shadows and partial occlusion, issues that are often encountered in video traffic sequences that are captured from a moving vehicle. These factors substantially degrade the performance of the existing traffic sign recognition (TSR) systems and in this paper we detail the implementation of a new strategy that entails three distinct computational stages. The first component addresses the robust identification of the candidate traffic signs in each frame of the video sequence. The second component discards the traffic sign candidates that do not comply with stringent shape constraints, and the last component implements the classification of the traffic signs using Support Vector Machines (SVMs). The main novel elements of our TSR algorithm are given by the approach that has been developed for traffic sign classification and by the experimental evaluation that was employed to identify the optimal image attributes that are able to maximize the traffic sign classification performance. The TSR algorithm has been validated using video sequences that include the most important categories of signs that are used to regulate the traffic on the Irish and UK roads, and it achieved 87.6% sign detection, 99.2% traffic sign classification accuracy and 86.7% overall traffic sign recognition.

A design of 10-bit 25-MS/s SAR ADC using separated clock frequencies with high speed comparator in 180nm CMOS

A design of a 10-bit 25 MS/s Successive Approximation Register (SAR) Analog to Digital Converter (ADC) that uses improved dynamic comparator has been introduced in this paper. In this improved dynamic comparator, a novel pre-amplifier is proposed in order to enhance the bandwidth up to 817 MHz when compared to classical pre-amplifier structures. Besides, a modified dynamic latch with driving simultaneously gate and bulk terminals are also presented in this work. The whole of SAR ADC is designed and simulated in 180nm CMOS process with the structure based on the conventional architecture but reduced the capacitor array mismatch by using separated clock frequencies to control simultaneously comparator and SAR combination logic. Thus, this design works with the clock frequency of 0.5 GHz achieving a maximum sampling rate at 25 MS/s and 1.8V supply voltage. Without calibration technique, sampling at 25 MS/s, peak DNL and peak INL of original ADCs averaged across the array are 0.7 least significant bit (LSB) and 3.6 LSB, respectively.

FPGA architecture of HMM-based decoder module in speech recognizer

This paper presents the reconfigurable architecture and implementation of HMM-based decoder module in speech recognizer on FPGA. The architecture is done with different parameters of speech recognition system that could be easily reconfigurable. The design and implementation on FPGA have been verified with utterances of 800 test speeches. The implementation results, the recognition accuracy results of up to 98% are also presented.

Two algorithms for detection of mutually occluding traffic signs

The robust identification of the traffic signs represents the first and one of the most important steps in the development of a traffic sign recognition (TSR) system. Traffic signs detection usually involves a color segmentation process that uses the information related to the chromatic properties of the road signs. Since the traffic video data is captured in diverse road and weather conditions, the problem relating to traffic sign detection is quite challenging. Among several issues that need to be addressed during this processing stage, the problem generated by mutually occluding traffic signs (mutual occlusion occurs when one traffic sign partially occludes the surface of other road signs) that are attached to the same pole require special attention. In these situations the color segmentation process fails to correctly identify the regions that are associated with the traffic signs. These traffic sign detection failures compromise the performance of other stages of the TSR system and in this paper we propose two approaches that address the segmentation of mutually occluding traffic signs. The first approach uses the information associated with the inner parts of the traffic signs, while the second approach applies the watershed transform to identify the signs that have their borders in contact or are mutually occluding.

An Effective Architecture of Memory Built-In Self-Test for Wide Range of SRAM

Together with highly increasing integration on one chip currently, usage of memories, mainly Static Random Access Memory (SRAM), applied to wide range of functions is inevitable. However, memory faults are greatly concerned due to purpose of achieving high yield. As a result, a memory built-in self-test (MBIST) has become essential in any system obviously. As regards MBIST, while increasing criteria associating with area, frequency as well as various test algorithms has posed, current approaches have not adapted both such silicon requirements and ability of covering errors with complex algorithms yet. In this work, an effective architecture of MBIST for SRAM type with different configurations is proposed for not only ensuring high ability of detecting memory faults supported by the most popular algorithms namely MARCH C-and TLAPNPSF but also satisfy strict silicon criteria. Indeed, achieving great performance based on necessary experiments on 130nm technology with Application Specific Integrated Circuit (ASIC) design flow has confirmed strong competition to current designs.

A High Performance Dynamic ASIC-Based Audio Signal Feature Extraction (MFCC)

State-of-the-art speech recognition, speech analysis as well as music modeling have approached Mel-Frequency Cepstral Coefficient (MFCC) and confirmed great performance in comparison to other feature extractions. Based on obtained software performance, a wide range of hardware designs are applied to highly increasing integrated systems achieving real-time performance and ability of mobility. Nevertheless, most hardware approaches witnessing certain configurations have experienced limitation of functions due to fixed-point format, strict silicon requirements or exact applications, which is reasonable for low ability of reusing and high cost of product. As regards MFCC method, there are various concerning parameters such as number of samples, range of filter bands, Fast Fourier Transform (FFT) number, number of cepstrums or even different level of delta coefficients, which significantly affect final performance of entire applications. As a result, a dynamic ASIC-based MFCC hardware architecture is proposed in this paper in order to meet real-time system requiring high performance as well as confirm superiorities regarding to ability of reconfiguration feasibly through an Advance High-performance Bus (AHB) interface in chip level instead of modifying at Register Transfer Level (RTL) in developed duration. Besides, have not only experiments on 130nm technology with full ASIC design flow witnessed high frequency at 500MHz but applying IEEE 754 floating-point format has also confirmed great accuracy between hardware design and software design, which apply in certain application towards Vietnam automatic speech recognition (ASR).

An ASIC-Based Artificial Neural Network Applied Real-time Speech Recognition SOPC

Artificial Neural Network (ANN) is promoted to one of major schemes applied in pattern recognition area. Indeed, many approaches to software-based platforms have proven great performance of ANN. However, developing pattern recognition systems integrating ANN hardware-based architecture has been limited not only by the silicon requirements such as frequency, area, power, or resource but also by high accuracy and real-time applications strictly. Although a considerable number of ANN hardware-based architectures have been proposed currently, they have experienced a deprivation of functions due to both small configurations and ability of reconfiguration. Consequently, achieving an effective ANN hardware-based architecture so as to adapt to not only strict accuracy, enormous configures, or silicon area but also real-time criterion in pattern recognition systems has been really challenged. To tackle these issues, this work has proposed a dynamic structure of three-layer ANN architecture being able to reconfigure for adapting to various real-time applications. What is more, a complete SOPC system integrating proposed ANN hardware has also implemented to apply Vietnamese speech recognition automatically to confirm high recognition probability around 95.2 % towards 20 Vietnamese discrete words. Moreover, experiment results on such ASIC-based architecture have witnessed maximum frequency at 250 MHz on 130nm technology as well as great ability of reconfiguration.

Vietnamese speech synthesis with novel pairing phrase method built in embedded systems

Embedded systems are being further developed and applied in speech synthesizer. In the previous Text To Speech (TTS) systems, speech synthesis was only built in personal computer. In this paper, a TTS Vietnamese system with pairing phrase method based on embedded design is presented. The proposed system is built on BeagleBone Black and Embedded Linux. The prosodic quality is relatively well. The listener could understand the meaning of speech, and the proposed TTS system achieves asymptotic naturalness of speech.

Isolated vietnamese handwriting recognition embedded system applied combined feature extraction method

In this research, an embedded system approaching isolated Vietnamese handwriting upper case recognition is illustrated. Obtained results from experiments have experienced that proposed feature extraction method, a major step of complete character recognition scheme, combining contour profile and projection histogram techniques is superior to others. Furthermore, the full conceptual system performance is evaluated on the embedded system, namely BeagleBoard-xM board, to confirm that recognition probability is up to more 90% over 27000 characters over thirty different persons.