Tsai-Ming Hsieh

Technology remapping for engineering change with wirelength consideration

In this paper, we present an efficient approach to make functional change by using spare cells efficiently. The proposed approach includes two main steps (1) technology remapping and (2) spare cell selection. In technology remapping step, resource constraints will be considered to find a set of proper cells for remapping with examining resources exhaustively. In spare cell selection, we regard this problem as a question of resource allocation, the goal is to simultaneously select the suitable spare cells to achieve the functional changes and minimize the wirelength increases. We modify the matching algorithm to solve the spare cell selection with the goal of minimizing the increase in wire length, and use two wiring cost estimate methods to improve the wiring cost measurement of accuracy. Experimental results based on nine industry benchmarks show that there is 1% bias between the wiring cost our approach estimated and the actual wiring cost.

A new ECO technology for functional changes and removing timing violations

Engineering Change Order (ECO), is an effective technique for fixing circuit functionality and timing problems after the placement stage. We proposed a new approach to solve the function and timing problems simultaneously by rerouting the netlist to the spare cells. The proposed approach includes two stages (1) functional change with timing consideration and (2) timing optimization. In the first stage, a spare cell selection algorithm is designed to select proper spare cells which can solve the functional change problems with timing consideration. After the first stage, we conduct timing analysis to find paths which violated the timing constraints, and using gate sizing and buffer insertion techniques to remedy those paths. Experimental results are based on five industry benchmarks. The results show that our approach is effective and efficient in fixing the functional change problem and timing optimization problem.

A congestion-driven buffer planner with space reservation

In this paper, we present a new algorithm of the four-stage buffer planning to improve success rates of buffer insertion and wiring congestion. It is based on the space reservation, which reserves enough dead space between all adjacent blocks. First of all, we perform the space reservation between all adjacent blocks of an initial floorplan. Second, the shortest path graph is used to select the routing path for each net. Third, the algorithm finds all buffer locations which meet the timing constraints for all nets. Finally, compact the layout to delete the redundant area. Compared to the traditional method, such as channel insertion, our algorithm can reserve enough silicon space for buffer insertion without moving blocks which lead to a large re-computation and area expansion. Experimental results clearly show the superiority of our method to the traditional method without space reservation

A new congestion and crosstalk aware router

In this paper, we study and implement a new congestion- and crosstalk-driven routing system. It first takes estimated congestion cost, crosstalk cost and the track utilization of each routing grid simultaneously into consideration to determine the global routing paths of all nets. Then a crosstalk-driven track assignment algorithm is applied to the global routing result to generate the corresponding detailed routing solution. The proposed approach can effectively disperse nets to lower congested regions. Compared with the results of the maze routing algorithm without consideration of crosstalk and the crosstalk aware routing solution, our algorithm achieves 94% and 17% reduction of the overall effective coupling length on average, respectively.

Timing-driven X-architecture router among rectangular obstacles

In this paper, we formulate a timing-driven obstacle-avoiding X-architecture Steiner minimal tree (TOA-XSMT) problem, and propose a timing-driven routing tree construction which simultaneously minimizes the maximum source-to-terminal delay and the total wirelength. First, we construct a spanning graph by the terminals and the obstacles. Second, a minimal spanning tree is obtained in a spanning graph. Third, we transform a spanning tree into a feasible X-architecture tree. Fourth, for each terminal of the routing tree, the delay is computed by a modified Elmore delay model. Fifth, an efficient rerouting method is used to improve all timing violations which their delay are over a user-defined threshold. Finally, the critical terminals are rerouted by splitting and merging procedure. Compared to the result without rerouting, the maximum source-to-terminal delay is reduced by 60.8% with the 0.7% additional total wirelength.

Unified approach for simultaneous functional and timing ECO

Engineering change order (ECO) is a technique commonly used in the later integrated circuit design stages to reduce redesign efforts and time-to-market. ECO problems are generally categorised according to functional changes (functional ECO) or timing violations (timing ECO). This study differs from conventional approaches in its adoption of a solution that involves unifying functional ECO with timing ECO. The authors applied the concept of virtual nodes to the problem of transforming timing ECO into functional ECO. In addition to buffer insertion and gate sizing, the authors developed a novel detour reduction method for the repair of timing violation paths. Technology mapping is used to facilitate the selection of spare cells, through the generation of various revisions for each ECO. The unified ECO problem is then solved using a novel modification of the Hungarian matching algorithm. Experiment result demonstrates the efficacy of the proposed approach at solving both types of ECO simultaneously.

A logic difference generator with spare cells consideration for ECO synthesis

As the advance of IC manufacturing, the IC complexity is getting more and more complicated. Lots of existing designs and intellectual property (IP) are widely reused. Different from remaking a whole new chip, reusing existing designs or IP can release the pressure of time-to-market and save money. By utilizing logic difference technique, IC designer can identify differences between old and new circuits and output several engineering change orders (ECO) for functional change. Therefore, the quality of engineering changer orders will affect the functional change result. To the best of our knowledge, the success or failure of the functional change is depended on spare cells not the number of engineering change orders. Hence, this paper proposed a logic difference technique which considers the distribution of spare cells primarily. The experimental results show that our proposed algorithm has more engineering change orders than traditional logic difference technique, but it can achieve better result in wirelength and success rate after functional ECO.

Structural decomposition with functional considerations for low power

In this paper we present an approach to minimize power consumption in the logic synthesis stage by using the gate decomposition technique. Since the power consumption of ICs is not only decided by the switching activity of each gate but also depends on the gate types in the target library, the major difference between our algorithm and the traditional methods is that we consider the power consumption of different types of gate. In addition, by the usage of inverter relocation based on Demorgans law, we can further reduce the ICs total power consumption. Under the cases of different of input signal probabilities, switching rates are applied, and experimental results show that our approach can further reduce average power consumption by up to 12.7% as compared to the case of the applied ExDecomp/HeuDecomp algorithm (Twari et al, Proc. 30th Design Automation Conf., pp.74-79, 1993).