Tsunehisa Doi
Fujitsu
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Publication
Featured researches published by Tsunehisa Doi.
architectural support for programming languages and operating systems | 1994
Kenichi Hayashi; Tsunehisa Doi; Takeshi Horie; Yoichi Koyanagi; Osamu Shiraki; Nobutaka Imamura; Toshiyuki Shimizu; Hiroaki Ishihata; Tatsuya Shindo
The scalability of distributed-memory parallel computers makes them attractive candidates for solving large-scale problems. New languages, such as HPF, FortranD, and VPP Fortran, have been developed to enable existing software to be easily ported to such machines. Many distributed-memory parallel computers have been built, but none of them support the mechanisms required by such languages. We studied the mechanisms required by parallelizing compilers and proposed a new architecture to support them. Based on this proposed architecture, we developed a new distributed-memory parallel computer, the AP1000+, which is an enhanced version of the AP1000. Using scientific applications in VPP Fortran and C, such as NAS parallel benchmarks, we simulated the performance of the AP1000+.
international conference on supercomputing | 1995
Tatsuya Shindo; Hidetoshi Iwashita; Tsunehisa Doi; Junichi Hagiwara; Shaun Kaneshiro
High Performance Fortran (HPF) is a candidate for a standard programming language for distributed memory parallel computers. This paper presents the design and implement ation of an HPF compiler for the Fujitsu AP1OOO parallel computers. There are two novel features implemented in the compiler. The first is a machine-independent optimization based on the intermediate format. The second is a code generation technique utilizing the direct remote data access (DRDA) mechanism and stride data transfer supported by the AP1OOO hardware. With the results of experiments on the AP1OOO, this paper shows the effects of the optimization and code generation techniques.
international conference on supercomputing | 1994
Tatsuya Shindo; Hidetoshi Iwashita; Shaun Kaneshiro; Tsunehisa Doi; Junichi Hagiwara
This paper proposes twisted data layout as a novel and efficient data layout technique for distributed memory parallel processors (DMPP). Data layout is an important aspect in efficiently executing a parallel program on DMPPs. The optimal data layout pattern for an array may differ throughout the program. Twisted data layout can be used to resolve the conflicts among the optimal array distributions in a special case. Experimental results on the AP1000 multicomputer measure the performance of the twisted data layout scheme.
Proceedings. Third Working Conference on Massively Parallel Programming Models (Cat. No.97TB100228) | 1997
Junichi Hagiwara; Tsunehisa Doi; Tatsuya Shindo; Yoshinori Yaginuma; Kazuho Maeda
Recently, commercial parallel applications became important in parallel computing with the increase of parallel computer users. In this study, we parallelize two commercial applications, a fulltext search system and a data mining system. In this paper, the implementation of each application and its performance evaluation on the AP3000 parallel computer are shown. A parallel framework, a novel parallelizing approach applied to those applications, is also described.
Archive | 1998
Tsunehisa Doi; Ikuo Miyoshi; Takeshi Sekine; Tatsuya Shindo
Archive | 2014
Tsunehisa Doi
Archive | 2006
Toshiki Tanaka; Hideyuki Miyata; Kouichirou Amemiya; Tsunehisa Doi; Takao Naito
Archive | 2005
Tsunehisa Doi; Toshihiro Ozawa
Archive | 2010
Tsunehisa Doi; Shingo Tanino
Archive | 2006
Kouichirou Amemiya; Toshiyuki Shibuya; Tsunehisa Doi; Toshiki Tanaka; Hideyuki Miyata; Yasutaka Taniuchi