Tsung-Han Tsai

A Hardware/Software Co-Design of MP3 Audio Decoder

The Moving Picture Experts Group (MPEG) audio coding standard offers three levels of compression algorithms where the MPEG Layer III (MP3) has the best quality but with the most complexity. There are several complex coding techniques involved in MP3 audio decoding algorithm, therefore, it is difficult to make an efficient architecture design. This paper presents a hardware/software co-design method for the implementation of MP3 audio decoder, which meets the real-time requirement of MP3 standard. The software and hardware part of this decoder is partitioned into a pre-processing and a post-processing unit respectively. The pre-processing unit with a programmable parser processor is developed for the implementation of intensive decision making operations needed for audio bitstreams. The post-processing unit with a dedicated hardware of modified fast algorithm is designed for the regular and computation-intensive operations in MP3 audio decoding flow. The architecture achieves a high throughput with a reduced memory requirement and hardware complexity. With a two-level pipeline approach, it allows a high hardware utilization and is suitable to low power implementation. The proposed decoder system has been designed and implemented using VLSI cell-based approach. The die size is 3.5 × 4.45 mm2 with the maximum operation frequency of 20 MHz.

Error Reduction on Automatic Segmentation in Microarray Image

DNA Microarray hybridization is a popular high throughput technique in academic as well as in industrial genomics research. The Microarray image is considered as an important tool and powerful technology for large-scale gene sequence and gene expression analysis. There are many methods to analyze the Microarray image by automatic segmentation or gridding spot. These methods always have the same problem of noise and tilt in spot array. It is difficult to process strong noise image in automation. In this paper, we can reduce the error of the edge detection which is influenced by noise and tilt spot array. We propose an automatic segmentation method with some techniques from video segmentation to process the Microarray image. By the proposed method, we can reduce the automatic spot segmentation errors and get more exact spot position. Our method has the advantages of low computation and easy implementation. Eventually, we compare the result with ScanAlyze tool since ScanAlyze tool extracts spot position and edge by artificial interface. We obtain the 1.43% average differential value of spots analysis ratio in result with ScanAlyze.

Design and Implementation of a Joint Data Compression and Digital Watermarking System in an MPEG-2 Video Encoder

With the rapid distribution of digital video capture devices, significant videos can be captured effortlessly. The captured videos are often saved in moving pictures expert group-2 (MPEG-2) format. To prove copyright ownership, applying watermarking in MPEG-2 videos is necessary. However, little research has been devoted to the watermarking design not only for the spatial domain but also for the frequency domain and the realization of watermarking hardware. Thus, a joint data compression and watermarking system with configurable spatial and frequency domain embedding, and its very large scale integrated circuit (VLSI) architecture is presented in this paper. First, after analyzing the characteristics of videos, a novel watermarking system with two number-based keys and a shuffled image is built. It is based on the spread spectrum techniques and adaptive human visual system (AHVS). With a consideration of the cost and easiness of use, the proposed system is realized as blind detection which can dispense without the storage of the original-multimedia data. Second, the efficient VLSI architecture of our approach is designed. Various subjective and objective evaluations are performed for watermarking analysis. From the evaluation, it is realized that the system can achieve robust watermarking with high flexibility for joint data compression and low hardware complexity. Various attacks and comparisons also show the efficiency of the proposed watermarking scheme. Furthermore, the VLSI synthesis results demonstrate the high performance of the proposed architecture. Thus, the proposed system is adequate for a specific function intellectual property (IP) combined with a real-time video capture and a surveillance system.

A Low-Latency Multi-layer Prefix Grouping Technique for Parallel Huffman Decoding of Multimedia Standards

Huffman coding is a popular and important lossless compression scheme for various multimedia applications. This paper presents a low-latency parallel Huffman decoding technique with efficient memory usage for multimedia standards. First, the multi-layer prefix grouping technique is proposed for sub-group partition. It exploits the prefix characteristic in Huffman codewords to solve the problem of table size explosion. Second, a two-level table lookup approach is introduced which can promptly branch to the correct sub-group by level-1 table lookup and decode the symbols by level-2 table lookup. Third, two optimization approaches are developed; one is to reduce the branch cycles and the other is parallel processing between two-level table lookup and direct table lookup approaches to fully utilize the advantage of VLIW parallel processing. An AAC Huffman decoding example is realized on the Parallel Architecture Core DSP (PAC DSP) processor. The simulation results show that the proposed method can further improve about 89% of decoding cycles and 33% of table size comparing to the linear search method.

A Hardware/Software Co-design of High Efficiency AAC Audio Decoder

This paper presents an implementation of hardware/software co-design for high efficiency advanced-audio-coding (HE-AAC) audio decoder. The decoder system is partitioned into software and hardware part throughout the computation analysis. In our design strategy, the bitstream parser and lower complexity part are performed by software solution, and the higher complexity part is computed by hardware solution. As in the dedicated hardware, four units are developed to cope with IMDCT, analysis quadrature mirror filterbank (AQMF), HF generator and envelope adjuster and synthesis quadrature mirror filterbank (SQMF). To support the various types of transformation-based functions in HE-AAC decoding, we manipulate it based on the decomposition of common radix-2 FFT method. The hardware part is designed as an intellectual property (IP) by TSMC 90xa0nm library. As a cost-effective design, it consumes about 150xa0K gates and executes at a very low operation frequency with 1.75xa0MHz. The power consumption is only 7.69xa0mW with some low power design considerations. Moreover we construct the overall system including the wrapper design and embedded platform as a system on a programmable chip (SOPC) platform. With this design approach, over 91.26xa0% processor-based loading can be saved and substituted by this hardware IP.

Guest Editorial: Special Issue on Computing Architectures for Real-Time Video/Image Analysis

In recent years, video and image analysis tools have been increasingly employed in many real-time applications; these include lane and car recognition for intelligent transportation systems, human object segmentation and tracking for intelligent video surveillance systems, and face detection and image indexing for digital still cameras and camcorders. To implement these analysis tools in real-time applications, new computing architectures such as reconfigurable architectures, application-specific instruction-set processors, stream processing architectures, and dedicated processing elements have been developed to handle more complex real-time content analysis. It is often necessary to integrate specially designed hardware accelerators with other processors to achieve a high processing speed. Furthermore, new algorithms that are suitable for hardware design or implementation on existing architectures play important roles in such systems. The purpose of this special issue is to report on new hardware design ideas to support these video and image analysis tools. This special issue contains two parts. The first part describes computing platform design, including vision processors and memory sub-system design. The second part describes several design case studies of image and video analysis systems, including machine learning engines and video segmentation engines. The first part begins with two general-purpose vision processors with a single-instruction-multiple-data (SIMD) architecture that have been developed in the industry. These two new-generation designs both feature enhanced capabilities for processing higher-level video analysis tasks with different schemes. In “IMAPCAR: A 100 GOPS In-vehicle Vision Processor Based on 128 Ring Connected 4-Way VLIW Processing Elements,” Kyo and Okazaki design an in-vehicle vision processor with 128 8-bit four-way verylong-instruction-word (VLIW) RISC processing element (PE) array architecture. As compared to their previous design, IMAP-CE, the new design realizes 2.5 times better performance via the improved video I/O flexibility and data remapping structure, addition of one MAC unit per PE, and increased reliability of memory structure. In “Xetal-II: A Low-Power Massively-Parallel Processor for Video Scene Analysis,” Abbo, Kleihorst, and Schueler design a 140 GOPS image processor with a massively parallel SIMD (MP-SIMD) architecture comprising 320 PEs arranged as a linear processor array. To support regionbased processing, it provides a low-cost look-up table (LUT) and flag aggregation and flag-based result selection. In addition to computation engines, the design of memory sub-systems also plays an important role in a video and image analysis system. In “Streaming Data Movement for Real-Time Image Analysis,” Lopez-Lagunas and Chai propose the notion of stream descriptors as a means to define image stream access patterns and to improve memory access efficiencies by discovering the locality between different data streams. Examples are provided with a Reconfigurable Streaming Vector Processor (RSVP), and the design concept can be widely applied on different computing platforms such as ASIC and reconfigurable hardware. The second part describes four case studies that target different computing platforms: FPGA, multi-core processor, reconfigurable processor, and hybrid computing platform. S.-Y. Chien (*) National Taiwan University, Taipei, Taiwan e-mail: sychien@cc.ee.ntu.edu.tw

A high performance foreground detection algorithm for night scenes

Foreground detection is designed to separate the objects from a background scene. However, night scenes always contain high dynamic illumination variety so that the performance on detection drops largely. In this paper, we present a new foreground detection algorithm which is applicable to scenes with complicated illumination and shadow. This new algorithm utilizes multiple regions to perform background classification. Consequently human vision can focus on moving objects and the interferences such as night illumination or shadow can be effectively eliminated. Because this algorithm can eliminate most interference, therefore moving objects can be segmented more precisely. As our experiment, the precision of nigh scene foreground detection is highly improved compared with other techniques.

System Level Design and Implementation for Region-of-Interest Segmentation

Region-of-interested (ROI) segmentation is one of the important applications in content-based processing. Although much work has been done in this area, relatively little work has been reported to the ROI segmentation with an implementation consideration. This paper presents a system level design with edge-based ROI segmentation. In order to improve the overall system performance, we propose a computationally efficient algorithm to reduce the complexity in segmentation. Based on the algorithm level development, we put more efforts on the realization with a single board platform system. The system is based on the hybrid architecture, including the associating synchronous modules and asynchronous modules. Detailed task partitions are well scheduled. The system integrates the acquisition and visualization modules for video stream input and output, the transition module for video format transformation, and the DSP processing module for ROI segmentation. We also present a number of optimization techniques in fixed-point arithmetic, memory usage, data transfer and parallel processing. Experiments are performed in the dynamic natural environment. The proposed system can segment ROI well. The run-time results achieve 66 images per second on QCIF format and validate the perspective of using ROI segmentation in content-based applications.

Visual Hand Gesture Segmentation Using Signer Model for Real-Time Human-Computer Interaction Application

The task of automatic gesture segmentation is highly challenging due to the computational burden, the presence of unpredictable body motion and ambiguous nongesture hand motion. In this paper, a new approach is developed using Hausdorff based model tracking technique for the application of real-time human-computer interaction. This paper proposed a Three Phases Model Tracking approach, which consists of two main stages; one is motion history analysis, which classifies dynamic gesture into preparation, retraction and nucleus state based on temporal relationship. The other is model tracking, which tracks signer model and object model with different constraint based on the classified state. Finally, gesture model is extracted based on matching object model and signer model and the hand gesture region is segmented from the gesture model. Experiments are performed to test the robustness of gesture segmentation under various hand scale and complex background. The segmentation error rate and computational complexity are also analyzed to demonstrate that the proposed Three Phases Model Tracking approach can be applicable to real-time human-computer interaction system.

Low power techniques for MP3 audio decoder using subband cut-off approach

In this paper low power techniques for MP3 audio decoder are used based on a phenomenon of zero-filled subbands. By our analysis, large part of subbands contains useless zero-valued data, which can be cut-off. We propose an effective architecture to gain incremental improvements in power consumption and computation complexity. In DWIMDCT block, the computational complexity can be reduced to 34% when we combine the subband cut-off technique and our proposed fast algorithm. In SIMDCT block of synthesis filterbank, the same technique can be applied and the computational complexity can be reduced to 17%. This subband cut-off approach is simple and can be easily integrated with other designs.