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Dive into the research topics where Tsung-Yang Liow is active.

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Featured researches published by Tsung-Yang Liow.


IEEE Journal of Selected Topics in Quantum Electronics | 2010

Silicon Modulators and Germanium Photodetectors on SOI: Monolithic Integration, Compatibility, and Performance Optimization

Tsung-Yang Liow; Kah-Wee Ang; Qing Fang; Junfeng Song; Yong-Zhong Xiong; Mingbin Yu; Guo-Qiang Lo; D. L. Kwong

Si modulators and Ge photodetectors are monolithically integrated on Si-on-insulator. The carrier-depletion-type Si modulators achieved high modulation efficiency and speed (<i>V</i> <sub>¿</sub> <i>L</i> <sub>¿</sub> = 2.56 V·cm, 10 Gb/s). Low-voltage operation (<i>V</i> <sub>RF</sub> = 1 <i>V</i> <sub>pp</sub>) was also demonstrated. Introducing a low-thermal-budget postepitaxy anneal improves the performance of the Ge photodetectors, thus resulting in significantly improved dark current. The responsivity and speed in the low-voltage regime are also enhanced, which enhances low-voltage or even short-circuit (<i>V</i> <sub>Bias</sub> = 0 V) operation.


IEEE Journal of Selected Topics in Quantum Electronics | 2014

Review of Silicon Photonics Foundry Efforts

Andy Eu-Jin Lim; Junfeng Song; Qing Fang; Chao Li; Xiaoguang Tu; Ning Duan; Kok Kiong Chen; Roger Poh Cher Tern; Tsung-Yang Liow

Silicon photonics have progressed to a point where the next step for commercialization depends on the accessibility of manufacturing foundries. The implementation of a fabless foundry model using standardized process technology platforms is crucial for that to occur. Research and development (R&D) foundries are beginning to play bigger roles in transforming silicon photonics into a mature technology for mass production. R&D foundry services such as multi-project wafer (MPW) shuttles, customized process developmental runs and small volume manufacturing are discussed. The development of commercial foundries for low cost, high volume production is also shown to be underway, and key results from an on-going effort to set-up a manufacturing silicon photonics foundry line are presented.


Optics Express | 2012

Ultralow drive voltage silicon traveling-wave modulator

Tom Baehr-Jones; Ran Ding; Yang Liu; Ali Ayazi; Thierry Pinguet; Nicholas C. Harris; Matt Streshinsky; Poshen Lee; Yi Zhang; Andy Eu-Jin Lim; Tsung-Yang Liow; Selin Hwee-Gee Teo; Guo-Qiang Lo; Michael Hochberg

There has been great interest in the silicon platform as a material system for integrated photonics. A key challenge is the development of a low-power, low drive voltage, broadband modulator. Drive voltages at or below 1 Vpp are desirable for compatibility with CMOS processes. Here we demonstrate a CMOS-compatible broadband traveling-wave modulator based on a reverse-biased pn junction. We demonstrate operation with a drive voltage of 0.63 Vpp at 20 Gb/s, a significant improvement in the state of the art, with an RF energy consumption of only 200 fJ/bit.


Journal of Lightwave Technology | 2010

Monolithic Polarization and Phase Diversity Coherent Receiver in Silicon

C.R. Doerr; Peter J. Winzer; Young-Kai Chen; S. Chandrasekhar; Mahmoud Rasras; Long Chen; Tsung-Yang Liow; Kah-Wee Ang; Guo-Qiang Lo

In this paper, we realized a monolithic silicon photonic integrated circuit (PIC) for polarization and phase diversity coherent detection. The PIC includes two polarization beam splitters, two 90° optical hybrids, and four pairs of balanced photodiodes implemented as integrated germanium detectors. We tested the PIC using polarization-division multiplexed quadrature phase-shift keyed signals at 43 and at 112 Gb/s.


IEEE Electron Device Letters | 2009

Sulfur-Induced PtSi:C/Si:C Schottky Barrier Height Lowering for Realizing N-Channel FinFETs With Reduced External Resistance

Rinus T. P. Lee; Andy Eu-Jin Lim; K. L. Tan; Tsung-Yang Liow; D. Z. Chi; Yee-Chia Yeo

In this letter, sulfur (S) segregation was exploited to attain a record-low electron barrier height (PhiB N) of 110 meV for platinum-based silicide contacts. Sulfur-incorporated PtSi:C/Si:C contacts were also demonstrated in strained FinFETs with Si:C source/drain stressors. Incorporation of sulfur at the PtSi:C/Si:C interface in the source/drain regions of FinFETs provides a 51% improvement in external resistances and a 45% enhancement in drive current as compared to devices without S segregation. The remarkable reduction in PhiB N is explained using charge transfer and dipole formation at the silicide/semiconductor interface with S segregation.


Optics Express | 2010

WDM multi-channel silicon photonic receiver with 320 Gbps data transmission capability.

Qing Fang; Tsung-Yang Liow; Jun Feng Song; Kah Wee Ang; Mingbin Yu; Guo-Qiang Lo; Dim-Lee Kwong

A high performance monolithically integrated WDM receiver is fabricated on the SOI platform, with key components comprising a 1 x 32 Si-based AWG and an array of high speed waveguided Ge-on-Si photodetectors. The optical channel spacing is 200 GHz. This configuration was used to demonstrate 32-channel operation in the L-band, where it is particularly challenging for silicon photonics due to the low absorption coefficient of Ge at L-band wavelengths. Each channel is capable of operating at a data rate of at least 10 Gbps, resulting in an aggregate data rate of 320 Gbps. At a BER of 1 x 10(-11), the WDM receiver showed an optical input sensitivity between -16 dBm and -19 dBm.


IEEE Photonics Technology Letters | 2010

Low-Loss and Broadband Cantilever Couplers Between Standard Cleaved Fibers and High-Index-Contrast Si

Long Chen; C.R. Doerr; Young-Kai Chen; Tsung-Yang Liow

We demonstrate a novel facet coupler for coupling between 10.4-m mode-diameter cleaved fibers and high-index-contrast SiN or Si waveguides. By creating a cantilevered glass waveguide surrounding an inverse taper and injecting a low-index cladding around the cantilever, we demonstrate coupling loss as low as 0.7 dB/facet to 500 nm 400 nm Si N waveguides, with only 0.2-dB polarization-dependent loss and 0.4-dB wavelength-dependent loss from 1480 to 1580 nm. Coupling loss of 1.5-2.0 dB/facet to 500 nm 220 nm Si waveguides at 1550 nm is also demonstrated.


IEEE Photonics Technology Letters | 2011

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Qing Fang; Jun Feng Song; Tsung-Yang Liow; H. Cai; Mingbin Yu; Guo-Qiang Lo; Dim-Lee Kwong

In this letter, a 2 × 2 thermo-optic waveguide-based switch with ultralow power consumption is demonstrated and fabricated using a standard complementary metal-oxide-semi conductor (CMOS) process. The phase arms are suspended by removing adjacent SiO2 and 120 μm of the underlying Si, while leaving a few SiO2 beams to support the suspended phase arms for the purpose of structural strength. As compared to the switch without isolation layer, a significant reduction of >;98% in power consumption is achieved. It is realized by preventing the heat from leaking out of the phase arms due to the presence of the air isolation layer. Our device shows an extinction ratio of over 23 dB at 1550 nm for TE mode with an ultralow power consumption of 0.49 mW. The response time is 266 μs, including the raise time of 144 μs and the fall time of 122 μs.


Optics Express | 2012

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Xiaoguang Tu; Junfeng Song; Tsung-Yang Liow; Mi Kyoung Park; Jessie Quah Yiying; Jack Sheng Kee; Mingbin Yu; Guo-Qiang Lo

As the sensitivity and detection limit of photonic refractive index (RI) biosensor increases, the temperature dependence becomes a major challenge. In this paper, we present a Mach-Zehnder Interferometer (MZI) biosensor based on silicon nitride slot waveguides. The biosensor is designed for minimal temperature dependence without compromising the performance in terms of sensitivity and detection limit. With air cladding, the measured surface sensitivity and detection limit of MZI biosensor reach 7.16 nm/(ng mm(-2)) and 1.30 (pg mm(-2)), while achieving a low temperature dependence is 5.0 pm/° C. With water cladding, the measured bulk sensitivity and detection limit reach 1730(2π)/RIU and 1.29 × 10(-5) RIU respectively. By utilizing Vernier effect through cascaded MZI structures, the measured sensitivity enhancement factor is 8.38, which results in a surface detection limit of 0.155 (pg mm(-2)).


symposium on vlsi technology | 2006

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Tsung-Yang Liow; K. L. Tan; Rinus T. P. Lee; Anyan Du; Chih-Hang Tung; Ganesh S. Samudra; Won-Jong Yoo; N. Balasubramanian; Yee-Chia Yeo

We report the demonstration of 25 nm gate length L<sub>G</sub> tri-gate FinFETs with Si<sub>0.99</sub>C<sub>0.01</sub> source and drain (S/D) regions. The strain-induced mobility enhancement due to the Si<sub>0.99</sub>C<sub>0.01</sub> S/D leads to a drive current I<sub>Dsat</sub> improvement of 20% at a fixed off-state current I<sub>off</sub> of 1times10<sup>-7</sup> A/mum. With additional channel strain engineering, FinFETs incorporating Si<sub>0.99</sub>C<sub>0.01</sub> S/D and a tensile-stress silicon nitride (SiN) capping etch-stop layer (ESL) achieve an I<sub>Dsat</sub> enhancement of 56%

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