Tsutomu Sasao

Switching Theory for Logic Synthesis

From the Publisher: Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks. An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries. Switching Theory for Logic Synthesis is based on the authors lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies. Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

Logic Synthesis and Optimization

Notice that because fx ⊇ fx′ , fx + fx′ = fx. Complementing the above, fx = fx + fx′ = fx · fx′ . Hence the above is proved. Realize the significance of this operation. This allows you to compute the complement of a very large unate function by computing complements of the respective cofactors. The proof for f is -ve unate in x is similar. • If f is negative unate in x, then: f ′ = x · f ′ x + f ′ x (8)

Representations of Discrete Functions

Representations of Discrete Functions is an edited volume containing 13 chapter contributions from leading researchers with a focus on the latest research results. The first three chapters are introductions and contain many illustrations to clarify concepts presented in the text. It is recommended that these chapters are read first. The book then deals with the following topics: binary decision diagrams (BDDs), multi-terminal binary decision diagrams (MTBDDs), edge-valued binary decision diagrams (EVBDDs), functional decision diagrams (FDDs), Kronecker decision diagrams (KDDs), binary moment diagrams (BMDs), spectral transform decision diagrams (STDDs), ternary decision diagrams (TDDs), spectral transformation of logic functions, other transformations oflogic functions, EXOR-based two-level expressions, FPRM minimization with TDDs and MTBDDs, complexity theories on FDDs, multi-level logic synthesis, and complexity of three-level logic networks. Representations of Discrete Functions is designed for CAD researchers and engineers and will also be of interest to computer scientists who are interested in combinatorial problems. Exercises prepared by the editors help make this book useful as a graduate level textbook.

On the complexity of mod-2l sum PLA's

Consideration is given to the realization of logic functions by using PLAs with an exclusive-OR (EXOR) array, where a function is represented by mod-2 (EXOR) sum-of-products (ESOPs) and both true and complemented variables are used. The authors propose a new PLA structure using an EXOR array. They derive upper bounds on the number of products of this type of PLA that are useful for estimating the size of a PLA as well as for assessing the minimality of the solutions obtained by heuristic ESOP minimization algorithms. Computer simulation using randomly generated functions shows that PLAs with the EXOR array require, on the average, fewer products than conventional PLAs. For symmetric functions, the authors conjecture that the PLAs with an EXOR array require, at most, as many products as the conventional PLAs. The proposed PLAs can be made easily testable by adding a small amount of hardware. >

Logic Synthesis and Verification

Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references.

And-Exor Expressions and their Optimization

This chapter consists two parts: the first part presents 7 classes of AND-EXOR expressions:positive polarity Reed-Muller expressions, fixed polarity Reed-Muller expressions, Kronecker expressions, pseudo Reed-Muller expressions, pseudo Kronecker expressions, generalized Reed-Muller expressions and exclusive-or sum-of-products expressions (ESOPs). Relations between these classes are shown. The number of products to realize several classes of functions are analyzed. Optimization programs for these expressions were developed, and statistical results for arithmetic functions, randomly generated functions, and all the functions of 4 and 5 bariables were obtained. The second part presents an optimization method for pseudo-ronecker expressions using ternary decision diagrams (TDDs). The conventional method requires memory of O(3n) to simplify an n-variable expression, and is only practical for functions of up to n = 14 variables. The method presented here uses TDDs, and can optimize considerably larger problems. Experimental results for up to n = 39 variables are shown.

FPGA Design by Generalized Functional Decomposition

A method for designing look-up table type Field Programmable Gate Arrays (FPGAs) by functional decomposition is presented. Look-up table type FPGAs consist of 5-input Lookup-Tables (LUTs) interconnected by programmable wiring. Main subjects are 1) Generalized functional decomposition using BDDs; 2) Realization of functions by 5-input LUTs; 3) Design algorithm; and 4) Comparison with other systems. Preliminary version of the program produced solutions competitive to the previously published methods. For example, the present design method produced the circuits with 8 and 11 LUTs for sym9 and rd84, respectively.

A method to represent multiple-output switching functions by using multi-valued decision diagrams

Multiple-output switching functions can be simulated by multiple-valued decision diagrams (MDDs) at a significant reduction in computation time. analyze the following approaches to the representation problem: shared multiple-valued decision diagrams (SMDDs), multi-terminal multiple-valued decision diagrams (MTMDDs), and shared multi-terminal multiple-valued decision diagrams(SMTMDDs). For example, we show that SMDDs fend to be compact, while SMTMDDs tend to be fast. We present an algorithm for grouping input variables and output functions in the MDDs.

Spectral Transform Decision Diagrams

This chapter proposes spectral decision diagrams (STDDs), that are graphical representations of spectral transforms of switching functions and integer-valued functions. Binary decision diagrams (BDDs) and functional decision diagrams (FDDs) are graphical representations for switching functions and their Reed-Muller transforms, respectively. Multi-terminal decision diagrams (MTBDDs), arithmetic transform decision diagrams (ACDDs), and Walsh transform decision diagrams (WDDs) are graphical representations for integer-valued functions, their arithmetic transforms, and their Walsh transforms, respectively. This chapter shows that an STDD represents a function and its spectral transform at the same time. As for n-bit adders, ACDDs and WDDs require O(n) nodes while MTBDDs require O(2 n ) nodes. As for n-bit multipliers, ACDDs and WDDs require O(n 2) nodes while MTBDDs require O(4 n ) nodes.

Selection of potentially testable path delay faults for test generation

We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing untestable paths from consideration. Test generation is also applied as part of the proposed method. We demonstrate the effectiveness of the method by presenting results for benchmark circuits.