Tsuyoshi Arigane

Constant-charge-injection programming: a novel high-speed programming method for multilevel flash memories

Constant-charge-injection programming (CCIP) has been proposed as a way to achieve high-speed multilevel programming in flash memories. In order to achieve high programming throughput in multilevel flash memory, programming method must provide: 1) high-speed cell-programming; 2) high programming efficiency; and 3) highly uniform programming characteristics. Conventional source-side channel-hot-electron injection (SSI) programming realizes both fast cell-programming and high programming efficiency, but the large cell-to-cell variation in programming speed with SSI is a problem. CCIP reduces the characteristic variation of SSI programming and satisfies all of the above requirements. By applying CCIP to 2-bit/cell AG-AND flash memory, the high programming throughput of 10.3 MB/s is obtained with no area penalty. This is 1.8 times faster than the throughput with conventional SSI programming.

A 130-nm CMOS 95-mm 2 1-Gb Multilevel AG-AND-Type Flash Memory with 10-MB/s Programming Throughput

A 1-Gb AG-AND flash memory has been fabricated using 0.13-μm CMOS technology, resulting in a cell area of 0.104 μm 2 and a chip area of 95.2 mm 2 . By applying constant-charge-injection programming and source-line-select programming, a fast page programming time of 600μs is achieved. The four-bank operation attains a fast programming throughput of 10 MB/s in multilevel flash memories. The compact SRAM write buffers reduce the chip area penalty. A rewrite throughput of 8.3 MB/s is achieved by means of the RAM-write operation during the erase mode.

Selective-Capacitance Constant-Charge-Injection Programming Scheme for High-Speed Multilevel AG-AND Flash Memories

The market for flash memories has emphasized bit-cost reduction and high programming throughput because of demanding applications such as high quality digital still cameras and portable video recorders. One of the solutions to achieve low cost-per-bit is the multilevel cell (MLC) technique. However, the MLC technique requires precise control of the memory cells threshold voltage (V/sub th/). A V/sub th/ distribution of a multilevel (four-level) memory cell is presented. When the memory cell is programmed to a higher level, program/verify operations must be performed to yield a narrow V/sub th/ distribution. Therefore, particular attention is paid to suppress the deviations of the programming characteristics in order to reduce the number of those operations and enhance programming throughput. To suppress the deviations, constant-charge-injection programming (CCIP) has been developed in assist-gate (AG)-AND flash memories. At the 90-nm node, however, this technique is insufficient. In this paper, we present a new highspeed multilevel programming method called selective-capacitance CCIP scheme that has achieved a programming throughput of 10 MB/s in 4-Gbit multilevel AG-AND flash memory.

A 126 mm 2 4-Gb Multilevel AG-AND Flash Memory with Inversion-Layer-Bit-Line Technology

A 4-Gb AG-AND flash memory was fabricated by using a 90-nm CMOS technology. To reduce cell size, an inversion-layer-bit-line technology was developed, enabling the elimination of both shallow trench isolations and diffusion layers from the memory cells. The inversion-layer-bit-line technology combined with a multilevel cell technique achieved a bit area 2F 2 of 0.0162μm 2 , resulting in a chip size of 126mm 2 . Both an address and temperature compensation techniques control the resistance of the inversion-layer local bit line. Source-side hot-electron injection programming with self-boosted charge, accumulated in inversion-layer bit lines under assist gates, reduces the dispersal of programming characteristics and also reduces the time overhead of pre-charging the bit lines. This self-boosted charge-injection scheme achieves a programming throughput of 10MB/s.