Tsuyoshi Yakihara

A series of InGaP/InGaAs HBT oscillators up to D-band

In this paper, the development of a series of fixed-frequency heterojunction bipolar transistor (HBT) oscillators from the W- to D-bands is reported. The oscillators are designed based on feedback theory with a small-signal equivalent circuit. This design method enables the achievement of high-output-power oscillators for the management of the power that is generated at the current source inside the HBT. We use a 1 /spl mu/m/spl times/10 /spl mu/m single-emitter InGaP/InGaAs HBT as an active device for each oscillator, and 50-/spl Omega/ coplanar waveguides as transmission lines and resonators. Emitter output topology is adopted to reduce the chip size. The series of oscillators achieve the oscillation frequency of 74.8-146.7 GHz. To our knowledge, the 146.7-GHz fundamental oscillation frequency is the highest oscillation frequency achieved thus far using InGaP/InGaAs HBT technology. The output power of the 146.7-GHz oscillator is -18.4 dBm. The chip size of the oscillator is 731 /spl mu/m/spl times/411 /spl mu/m.

Monolithic sampling head IC

A monolithic sampling head IC composed of a resonant tunneling diode (RTD) for the sampling pulse generator and Schottky barrier diodes for the sampling bridge has been developed. The RTD was made using an In/sub 0.53/Ga/sub 0.47/As-AlAs structure (pseudomorphic strained superlattice). For this type of high switching voltage RTD, a peak-to-valley ratio (P/V ratio) of 9 at 202 degrees C peak-to-peak switching voltages of 1.5 V or more at room temperature were achieved. The Schottky barrier diodes were made from an (In/sub 0.53/Ga/sub 0.47/As)/sub 0.5/(In/sub 0.52/Al/sub 0.48/As)/sub 0.5/ compound. A frequency bandwidth of at least 26 GHz was obtained. When attempting to use a quantum effect device (such as an RTD) in a practical application, the most important factor to consider is its reliability. Good results were achieved in an endurance test of this device, in which it was made to continuously oscillate between 600 MHz to 1 GHz at 90 degrees C for more than 1000 h. >

Design consideration for folding/interpolation ADC with SiGe HBT

This paper describes the design and performance of a high-speed 6-bit ADC using SiGe HBT for measuring-instrument applications. We show that the Gummel-Poon model suffices for SiGe HBT modeling and then we describe that the folding/interpolation architecture as well as simple, differential circuit design are suitable for ADC design with SiGe HBT. Measured results show that the nonlinearity of the ADC is within /spl plusmn/1/2 LSB, and the effective bits are 5.2 bits at an input frequency of 100 MHz and 4.2 bits at 200 MHz with 768 MS/s. We also describe some design issues for folding/interpolation ADC.

System architecture and key components of a multi-Giga-Hertz A/D converter with HBT

This paper reports the design and performance of a very fast 6-bit ADC system with GaAs HBT technology. The ADC system consists of a track/hold circuit and an ADC. The track/hold circuit employs an open-loop architecture and uses Schottky barrier diodes for a diode switch, and achieves 3 GS/s operation with better than 6-bit linearity. The 6-bit ADC employs folding/interpolation architecture to reduce hardware and power maintaining the high-speed operation, and it achieves DC linearity better than 7-bit.

High-speed ADC systems with HBTs for measuring instrument applications

Abstract This paper presents very high-speed Analog-to-Digital Converter (ADC) systems for measuring instrument applications, and also related theoretical results. First we describe the design, testing and performance of ≈1 GS/s 6-bit and 7-bit ADCs using SiGe heterojunction bipolar transistor (SiGe HBT), and a 3 GS/s 6-bit ADC and Track/Hold (T/H) circuit using GaAs heterojunction bipolar transistor (GaAs HBT). We show that SiGe HBTs and GaAs HBTs have technological potential, and that the folding/interpolation architecture is suitable for high-speed ADC systems. Next, we derive three theoretical results aimed at very high-speed, wideband ADC systems. ⋅A folding/interpolation architecture is suitable for very high-speed ADCs implemented with HBTs, and digital error correction is required to improve their AC performance. We show an error correction algorithm, as well as its effectiveness and limitation for high-frequency inputs. ⋅Aperture jitter is crucial in wideband ADC systems, and we have derived very general results about aperture jitter effects of such systems. ⋅A time-interleave ADC system can realize very high-speed ADC system, but timing skews in the system degrade its overall accuracy. We have derived the error power corresponding to timing skews. Finally, we discuss several issues relating to standardizing the specifications of very high-speed ADCs targeted at measuring instrument applications.

10G bps burst-mode clock recovery with synchronization time of 50ps

We developed 10 Gbps burst-mode clock recovery IC with synchronization time of 50 ps. Using the IC with PIN-TIA PDs, an optical packet receiver which requires no preamble is also developed.

High-speed photodetectors for full-wavelength-band WDM transmission systems at 40Gb/s and beyond

The capacity of the WDM system can be increased by increasing the useable optical bandwidth or using the available bandwidth more efficiently since bit. Ultra-wide-band WDM transmissions with high bit rates in the full-WDM-wavelength range from the O to U bands (1260-1675 nm) are also very attractive for achieving high-capacity WDM transmission at low cost. This paper represents the high-speed photodetectors with a 3-dB bandwidth of more than 50 GHz for full-wavelength-band WDM transmission systems at 40Gb/s and beyond. The photodetector is a back-illuminated lattice-mismatched InGaAs PIN photodiode that we designed and fabricated to operate with a 3-dB cut-off frequency to values above 40 GHz, in the full-WDM-wavelength range from the O to U bands, by applying a small junction diameter and reduced the thickness of the light-absorbing InGaAs layer with a lattice-mismatch of +0.2% to InP. For our photodiode modules, a 3-dB bandwidth as high as 65 GHz was achieved at a bias voltage of 3 V and the responsivities at wavelengths of 1310, 1552 and 1670 nm were 0.6, 0.65 and 0.55 A/W, respectively. 40Gb/s receivers and 10Gb/s PIN/TIA modules were described as applications of the FWB-PDs. The photodiode modules operating up to the bandwidth of 50GHz and above in the full-WDM-wavelength range can drive the development to 40Gb/s WDM transmission systems using RZ or NRZ format and the additional new channels in the U band.

Recent Development of High-Speed Optical Switches and Receivers for 40-Gbps Next-Generation Networks

40-Gb/s optical packet label recognition, switching, and buffering using an optoelectronic logic module and a waveguide matrix optical switch module are demonstrated. The switch can achieve a high ON/OFF extinction ratio of 25-26 dB and a first switching time of less than 2 ns.

Full-WDM-band photodiode modules for optical communications at 40 Gb/s and beyond

This paper presents the first demonstration of the high-speed full-WDM-band photodiode modules for the WDM systems throughout the S (1460-1530 nm) to U (1625-1675 nm) bands with bit-rates up to 40 Gb/s or above.

Dispersion managed U-band discrete fiber Raman amplifiers for 43Gb/s WDM transmission

We evaluated the eye-patterns of 43Gb/s WDM signals, which were amplified by dispersion managed U-band discrete fiber Raman amplifiers employing highly nonlinear fiber. No degradation of the eye-patterns was observed by adjusting the dispersion.