Tyler Osborn

Low-Temperature Bonding of Copper Pillars for All-Copper Chip-to-Substrate Interconnections

A copper-to-copper bonding process was developed for an all-copper, chip-to-substrate interconnect technology. High aspect ratio polymer molds for electroplating were formed using a photodefinable polymer on both the chip and the substrate surfaces. Copper pillars were fabricated by electroplating metal in the polymer molds. The chip-to-substrate all-copper connections were formed by joining the two pillars with electroless copper plating followed by an anneal process. The copper-to-copper bonding of the high aspect ratio pillars does not require the use of solder or other noncopper metals. Mechanical shear force measurements were used to characterize the bonding process as a function of annealing conditions. Excellent bond strength of the electrolessly joined pillars was achieved with a 250°C anneal, with the bond strength of the copper pillar interconnects exceeding 148 MPa. High aspect ratio pillars can provide mechanical compliance, and the electroless fabrication method compensates for pillar misalignment and nonplanarity of the bonded surfaces.

All-Copper Chip-to-Substrate Interconnects Part I. Fabrication and Characterization

A fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output connections. Electroless copper plating followed by low-temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The ability to fuse the two copper surfaces at modest temperature and pressure is demonstrated. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180°C. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 μm could be overcome, resulting in good pillar-to-pillar bonding. Successful silicon-on-silicon and silicon-on-FR-4 bonding was achieved with no degradation of the organic board.

All-Copper Chip-to-Substrate Interconnects Part II. Modeling and Design

A fabrication technique involving electro- and electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at 180°C. The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate interconnects is modeled in this paper. The elastic, thermomechanical behavior and electrical performance of the chip-to-substrate interconnects are related to the geometric parameters of the pillars (pitch, diameter, and aspect ratio) and physical properties of the interconnects (yield stress, coefficient of thermal expansion, Youngs modulus, Poissons ratio, and electrical conductivity). The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48-100 μm and height of 508-657 μm are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38-100 μm diameter and height from 441 to 617 μm.

High-Frequency Chip Connections

Advanced interconnects will be required to keep pace with the increasing speed of future microelectronics.

Electroless Copper Deposition with PEG Suppression for All-Copper Flip-Chip Connections

A fabrication technique using electroless copper deposition has been used to produce all-copper chip-to-substrate connections. This process replaces solder by electrolessly joining copper pillars on a chip and substrate. Previously, solid copper-to-copper bonding was demonstrated using a known electroless copper bath followed by low temperature annealing at 180°C for 1 h in a nitrogen environment. Although the process feasibility was demonstrated, it was inherently slow and required excessive process time. In this paper, an acceleration-suppression approach to copper plating was used to achieve a rapid deposition of high quality copper in enclosed regions. Elevated temperature was used for acceleration along with poly(ethylene glycol) (PEG) suppression. High temperature increased the transport of reactants and products in spatially restricted regions, and the addition of PEG provided control of the deposition rate. This allowed a kinetically controlled deposition while still maintaining good quality copper deposits without excessive porosity. Plating rates as high 6 μm/h in the spatially restricted region between mated pillars were achieved.

Electroless Deposition and Characterization of PtxRu1−x Catalysts on Pt/C Nanoparticles for Methanol Oxidation

The electroless deposition of Pt x Ru 1―x catalysts using hydrazine dihydrochloride or formic acid as the reducing agent in a modified Leaman bath was investigated. The effect of potential on the Pt x Ru 1 ―x composition was investigated by potentiostatically depositing Pt x Ru 1―x thin films on gold from acidic chloride electrolytes at potentials between ―0.46 V and 0.34 V (versus normal hydrogen electrode). The physical characteristics and elemental composition of the deposits were determined. An empirical model for the deposition process was developed, taking into account reactant concentration, temperature, and surface potential. The model accurately characterized the deposit composition over a wide Pt/Ru range. The surface potential was estimated to be 0.15 V during electroless deposition using formic acid as the reducing agent based on the empirical model. Deviations from the model were found when hydrazine was used as the reducing agent due to the formation of solution phase ruthenium complexes with hydrazine.

Platinum-Glass Composite Electrode for Fuel Cell Applications

Thin-film electrodes for a low-power direct methanol fuel cell (DMFC) were prepared by incorporating carbon-supported Pt nanoparticles (Pt/C) into a silicon dioxide glass matrix. The SiO 2 matrix was prepared via a sol-gel technique where tetraethyl orthosilicate (TEOS) was hydrolyzed by H 2 O in the presence of methanol. The Pt/C was stirred into the sol and the resulting mixture was applied to a glass membrane substrate and cured. The resulting films were ∼ 2 μm thick. Scanning electron microscopy (SEM) images indicate that the Pt/C was well dispersed, forming glass-separated conductive islands with sheet resistances in excess of 5000 Ω/□. The catalyst islands were interconnected into a conductive sheet by electrolessly depositing platinum from an aqueous plating bath. The Pt/C-SiO 2 glass composite thin-film electrodes showed high methanol oxidation peak currents of ∼ 180 mA/cm 2 when immersed in 0.5 M H 2 SO 4 , 0.5 M methanol electrolyte. The composite electrode was also applied to the anode of a 1 cm 2 passive DMFC and compared to an equivalent passive DMFC with a traditional Nafion-based Pt anode electrode with 10 M MeOH at room temperature. The composite electrode DMFC showed a 50 mV higher open-circuit voltage than the Nafion electrode cell, and the current density was also modestly improved.

Deposition of PtxRu1-x Catalysts for Methanol Oxidation in Micro Direct Methanol Fuel Cells

Platinum-ruthenium electrodes (PtxRu1-x) have been prepared by elec- trochemical and electroless deposition and investigated as catalysts for the oxidation of methanol in acidic solutions. PtxRu1-x deposits were electrochemically deposited from acidic chloride electrolytes at potentials between -0.46 and 0.34 V (vs. NHE). The composition of the electrodeposit was estimated by energy dispersive X-ray spectroscopy and is a strong function of the electrode potential. An empirical model for the deposition process is presented and kinetic parameters are estimated and dis- cussed. Also, the methanol oxidation activity of the PtxRu1-x catalysts was character- ized by cyclic voltammetry in 1.0 M CH3OH, 1.0 M H2SO4 solutions. Electroless PtxRu1-x samples were prepared in a modified Leaman bath with hydrazine dihydrochloride as the reducing agent. The kinetic results for the electro- chemical deposition of PtxRu1-x were directly applied and the deposition potential was estimated as approximately 0.40 V.

Advanced Chip-to-Substrate Connections

Transistor scaling, shrinking the critical dimensions of the transistor, has led to continuous improvements in system performance and cost. Higher density of the transistors and larger chip size has also led to new challenges for chip-to-substrate connections. The pace of change in packaging and chip-to-substrate connections has accelerated because off-chip issues are increasingly a limiting factor in product cost and performance. Chip-to-substrate connections are challenged on many fronts, including number of signal input-output (I/O) connections, I/O that operate at high speed, power and ground I/O, and low cost.

All-copper chip-to-substrate interconnects: Bonding, testing, and design for electrical performance and thermo-mechanical reliability

A novel fabrication process has been developed and characterized to create all-copper chip-to-substrate input/output (I/O) connections. Electroless copper plating followed by low temperature annealing in a nitrogen environment was used to create an all-copper bond between copper pillars. The bond strength for the all-copper structure exceeded 165 MPa after annealing at 180degC. During the anneal process, a significant microstructural transformation in the bonded copper-copper interface was observed. The changes were correlated to an increase in the bond strength. The process was characterized with respect to in-plane misalignment of bond sites. Significant planar misalignment, greater than the diameter of the pillars, could be tolerated. Through-plane mismatches between the pillars (pillar gap) as large as 65 mum could be overcome resulting in good pillar-to- pillar bonding. Successful silicon-on-FR4 bonding was achieved with no degradation of the organic board. The mechanical compliance and electrical performance of copper pillar chip-to-substrate interconnects has been modeled. The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of 48 mum to 100 mum and height of 508 mum to 657 mum are mechanically compliant and have parasitic inductance and capacitance less than 300 pH and 8.8 fF, respectively. A polymer collar improves the design space to 38 mum to 100 mum diameter and height from 441 mum to 617 mum.