Tyrone Tai-On Kwok

On the design of a self-reconfigurable SoPC cryptographic engine

We present a SoPC (system-on-a-programmable-chip) embedded system featuring self-reconfigurable capability. It addresses the factors that limit the system performance when FPGAs are used to implement various encryption algorithms dynamically. The limiting factors are the data transfer rate between the host and the FPGA, and the reconfiguration latency. The results generated by the cryptographic engine reported show that in order to attain optimal performance, it is crucial to floor-plan the reconfigurable part of the FPGA.

On the design, control, and use of a reconfigurable heterogeneous multi-core system-on-a-chip

With the continued progress in VLSI technologies, we can integrate numerous cores in a single billion-transistor chip to build a multi-core system-on-a-chip (SoC). This also brings great challenges to traditional parallel programming as to how we can increase the performance of applications with increased number of cores. In this paper, we meet the challenges using a novel approach. Specifically, we propose a reconfigurable heterogeneous multi-core system. Under our proposed system, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of applications. We have built a prototype of the system using FPGAs. Experimental evaluation demonstrates significant system efficiency of the proposed heterogeneous multi-core system in terms of computation and power consumption.

Practical design of a computation and energy efficient hardware task scheduler in embedded reconfigurable computing systems

By utilizing massively parallel circuit design in FPGAs, the overall system efficiency, in terms of computation efficiency and energy efficiency, can be greatly enhanced by offloading some computation-intensive tasks which are originally executed in the instruction set processor to the FPGA fabric. In essence, a hardware task scheduler is needed. However, most of the work in the literature considers scheduling algorithms which are unable or difficult to be implemented using the design flows in current development platform. Moreover, little of the work takes energy consumption into consideration. In this paper, we present the design of a hardware task scheduler which takes energy consumption into consideration, and can be readily implemented using current design flows

On the Design of an SoPC Based Multi-Core Embedded System

Due to the advancements of VLSI technologies, we can put more cores on a chip, resulting in the emergence of multi-core embedded systems. This also brings great challenges to traditional parallel processing as to how we can increase the performance of applications with increased number of cores. In this paper, we meet the challenges using a novel approach. Specifically, we propose an SoPC (System-on-Programmable-Chip) based multi-core embedded system. Under our proposed system, in addition to conventional processor cores, we introduce dynamically reconfigurable accelerator cores to boost the performance of applications. We have built a prototype of the system using FPGAs. Experimental evaluation demonstrates significant system efficiency of the proposed system in terms of computation and power consumption.

Scale Out Teaching, Scale Up Learning: Professional development for e-teaching/learning

Advances in technology is revolutionizing the way we think and behave. As young digital natives come with a new way of learning, we, as educators, need to approach education from a new angle. In order to assist teachers with the transition from traditional teaching to engaging online teaching, Technology-Enriched Learning Initiative (TELI) in The University of Hong Kong has designed a blended-learning professional development course titled, “Interactive Online Learning”. In this paper, we describe how we used blended learning and learning analytics to foster engagement and demonstrate possibility and practicality of DIY online teaching.

Design and evaluation of parallel string matching algorithms for network intrusion detection systems

Abstract. Network security is very important for Internet-connected hosts because of the widespread of worms, viruses, DoS attacks, etc. As a result, a network intrusion detection system (NIDS) is typically needed to detect network attacks by packet inspection. For an NIDS system, string matching is the computation-intensive task and hence the performance bottleneck, since every byte of the payload of packets must be checked against numerous predefined signature strings, which may occur arbitrarily in the payload. In this paper, we present the design and evaluation of parallel string matching algorithms targeting hardware implementation on FPGAs and software implementation on multi-core processors. Experimental results show that, on a multi-processor system, the multi-threaded implementation of the proposed parallel string matching algorithm can reduce string matching time by more than 40%.

Energy Harvesting in Internet of Things

Powering billions of connected devices has been recognized as one of the biggest hurdles in the development of Internet of Things (IoT). With such a volume of tiny and ubiquitous smart physical objects in this new Internet paradigm, power cables or sizable battery packs are no longer a viable option to bring them online for years and decades. Energy harvesting, which enables devices to be self-sustaining, has been deemed a prominent solution to these constraints. This chapter provides a comprehensive review of IoT devices, from their roles and responsibilities, to the challenges of operating them autonomously in heterogeneous environments. The concepts, principles and design considerations for energy harvesting are introduced to aid researchers and practitioners to incorporate this key technology into their next applications.

Data-assisted instructional video revision via course-level exploratory video retention analysis

Since teachers are not physically present in an online class, instructional video is the major carrier of course contents in an online learning environment. This paper aims to investigate how course-level exploratory video retention analysis can be used for identifying moments with abnormal watching behaviors and revising videos for a higher video retention. We have empirically evaluated the effectiveness of video analysis and revisions, based on evaluating retentions of revised videos.