Tz. E. Ivanov

Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements

The off-state current in n- and p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) is investigated systematically by conduction measurements at various temperatures and low-frequency noise measurements at room temperature. It is demonstrated that the leakage current is controlled by the reverse biased drain junction. The main conduction mechanisms are due to thermal generation at low electric fields and Poole–Frenkel accompanied by thermionic filed emission at high electric fields. The leakage current is correlated with the traps present in the polysilicon bulk and at the gate oxide/polysilicon interface which are estimated from the on-state current activation energy data. Analysis of the leakage current noise spectral density confirms that deep levels with uniform energy distribution in the silicon band gap are the main factors in determining the leakage current. The density of deep levels determined from noise analysis is in agreement with the value obtained from conductance acti...

Conduction and low-frequency noise in high temperature processed polycrystalline silicon thin film transistors

The performance of n- and p-channel high-temperature processed polycrystalline silicon thin-film transistors (polysilicon TFTs) has been investigated by conduction and low-frequency noise measurements. The polysilicon films were doped by boron or phosphorus ion implantation at concentrations of about 6×1016 and 3×1017 cm−3, respectively, and hydrogenated by ion implantation of hydrogen. Undoped and nonhydrogenated polysilicon films were also used for comparison. Channel length reduction due to dopant diffusion from the source and drain contacts was found to affect the transistor conduction and its associated noise. Low-frequency noise measurements indicate that the noise power spectral density of the drain current is mainly due to carrier number with correlated mobility fluctuation. The experimental data reveal the presence of exponential band tails in both n- and p-channel hydrogenated undoped polysilicon TFTs. In nonhydrogenated boron doped n-channel devices, high density of band tails and deep levels a...

Hot-carrier phenomena in high temperature processed undoped-hydrogenated n-channel polysilicon thin film transistors (TFTs)

Abstract A study on hot-carrier phenomena in high temperature processed undoped and hydrogenated n-channel polysilicon thin film transistors (TFTs) is presented. First, stress conditions are determined by photon emission measurements during impact ionization condition. Next four stress regimes are performed. We distinguish two modes of stress conditions according to drain voltage during stressing: High drain voltage stress (HDVS) and low drain voltage stress (LDVS). Each of these modes gives different results when applied to our TFTs. During HDVS condition, two regimes are observed. First, hot-hole injection into the oxide occurs synchronically with interface-state generation. At a second stage, this mechanism saturates and electron injection through the polySi–SiO2 barrier takes place with less interface states generated. In contrast, during LDVS conditions no saturation of interface-state generation is observed and two regimes of transconductance degradation appear. The distribution in the gap of the stress-induced interface states is calculated by a known method. Finally, on- and off-state current stress was studied. Off-stressing affects mainly the gate oxide and is not accompanied by measurable impact ionization phenomena and thus no considerable interface-state generation.

Photon emission and related hot-carrier effects in polycrystalline silicon thin-film transistors

The photon emission induced by the drain avalanche in polycrystalline silicon thin-film transistors (polysilicon TFTs) has been studied in wide drain and gate voltage ranges. As the photon emission phenomenon is closely related to hot-carrier effects, the gate and drain bias conditions for maximum device degradation have been determined from measurements of the emitted light intensity. In n-channel polysilicon TFTs, the effects of bias stressing at the maximum light emission are related to hot-hole trapping into the gate oxide near the drain and to formation of acceptor-like interface states consisted of midgap states and band tails.

Empirical relationship between low-frequency drain current noise and grain-boundary potential barrier height in high-temperature-processed polycrystalline silicon thin-film transistors

The relationship between low-frequency drain current noise spectral density SI and grain-boundary potential barrier height Vb is investigated in high-temperature-processed polycrystalline silicon thin-film transistors. It is demonstrated that a general empirical relationship exists between SI and Vb indicating that the noise sources are located at the grain boundaries. The implications of the obtained relationship between SI and Vb from the practical viewpoint are discussed.

VACUUM DEPOSITED COPPER PHTHALOCYANINE THIN FILMS-STRUCTURE AND SURFACE MORPHOLOGY

Abstract The surface morphology and the structure has been studied of vacuum deposited copper phthalocyanine (CuPc) thin films formed by vapour deposition of CuPc on fixed substrates at room temperature. Scanning electron microscopy revealed a grain surface morphology. Subsequent annealing, increase in layer thickness and the angle and the rate of deposition raised the average grain size. The electron diffraction pattern and optical transmission spectra showed an α polycrystalline structure. The most fine-grained 10 nm and homogeneous layers had thicknesses below 250 nm and a growth rate of 0.2–0.8 nm\s. The study was directed towards the potential application of the vacuum deposited CuPc layers in gas sensors.

Oxide field enhancement corrected time dependent dielectric breakdown of polyoxides

Abstract Time-to-breakdown ( t bd ) of polysilicon/polyoxide/polysilicon structures is investigated on small and large area capacitors. The ln( t bd ) versus 1/ E ox projection lines are corrected by using an average oxide field enhancement factor for the interface polysilicon/thermally grown polyoxide. A field acceleration factor G≈320 MV / cm in the time-to-breakdown projection line is obtained. It is shown that the fast prediction of time-to-breakdown can be achieved with short stress time measurements in structures of different area.

Gas-sensitivity of SnO2 layers treated by rapid thermal annealing process

Abstract A rapid thermal annealing (RTA) treatment was used to improve the performance of ammonia sensors based on a MOSFET structure with a thin SnO2 layer used as a gate. RTA processes in vacuum with duration of 15–60 s and temperatures 600–800°C were applied. After thermal treatment samples are subjected to a cycle of successive steps with different environmental conditions in order to reveal the sensitivity, selectivity and reversibility of the response. It is found that the RTA process at 800°C, with duration of 60 s, rise time of 2 s and fall time of 4 s results in enhanced sensitivity to the active agent (NH3), reduced cross-sensitivity to water vapours (relative humidity) and improved reversibility of the devices response. This overall improvement of the performance is explained by surface changes of the SnO2 layer, provoked by the RTA process. Such changes are revealed by reflection high-energy electron diffraction (RHEED) and scanning electron microscopy (SEM).

Electrical stress in N- and P-channel undoped-hydrogenated polysilicon thin film transistors (TFTs)

We applied electrical stress in P- and N-channel polysilicon thin film transistors. N-channel devices exhibit two-step degradation with hot-hole injection into the gate oxide followed by electron injection. Stress in P-channel devices provides interesting results in order to clarify the physical mechanisms occurring during device aging.

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Abstract Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.