Tzuen Hsi Huang

Back-gate forward bias method for low-voltage CMOS digital circuits

The back-gate forward bias method suitable for present standard bulk CMOS processes has been promoted for low-voltage digital circuit application. A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the dc voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed. Guidelines for ensuring proper implementation of the method in a bulk CMOS process have been set up against latch-up, parasitic bipolar, impact ionization, and stand by current. Following these guidelines, a cost-effective low power, low-voltage, high-density mixed mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.

A 1 V 2.2 mW 7 GHz CMOS Quadrature VCO Using Current-Reuse and Cross-Coupled Transformer-Feedback Technology

A current-reused quadrature voltage-controlled oscillator (CR-QVCO) is proposed with the cross-coupled transformer-feedback technology for the quadrature signal generation. This CR-QVCO has the advantages of low-voltage/low-power operation with an adequate phase noise performance. A compact differential three-port transformer, in which two half-circle secondary coils are carefully designed to optimize the effective turn ratio and the coupling factor, is newly constructed to satisfy the need of signal coupling and to save the area consumption simultaneously. The quadrature oscillator providing a center frequency of 7.128 GHz for the ultrawideband (UWB) frequency synthesizer use is demonstrated in a 0.18 mum RF CMOS technology. The oscillator core dissipates 2.2 mW from a 1 V supply and occupies an area of 0.48 mm2. A tuning range of 330 MHz (with a maximum control voltage of 1.8 V) can be achieved to stand the frequency shift caused by the process variation. The measured phase noise is -111.2 dBc/Hz at 1 MHz offset from the center frequency. The IQ phase error shown is less than 2deg. The calculated figure-of-merit (FOM) is 184.8 dB.

60-GHz Millimeter-Wave Life Detection System (MLDS) for Noncontact Human Vital-Signal Monitoring

A first reported experimental study of a 60 GHz millimeter-wave life detection system (MLDS) for noncontact human vital-signal monitoring is presented. This detection system is constructed by using V-band millimeter-wave waveguide components. A clutter canceller is implemented in the system with an adjustable attenuator and phase shifter. It performs clutter cancellation for the transmitting power leakage from the circulator and background reflection to enhance the detecting sensitivity of weak vital signals. The noncontact vital signal measurements have been conducted on a human subject in four different physical orientations from distances of 1 and 2 m. The time-domain and spectrum waveforms of the measured breathing and heartbeat are presented. This prototype system will be useful for the development of the 60-GHz CMOS MLDS detector chip design.

Low-Voltage

This paper presents the design of a direct-injection divide-by-3 frequency divider operating at the K -band. The divider is implemented in a 0.18- μm CMOS process. The measured free-running frequency of the divider is 7.96 GHz. By utilizing a floating-source differential injector and without a varactor tuning in the divider core, the total locking range is 3.2 GHz with a power consumption of 8.28 mW from a supply voltage of 0.9 V. The total power consumption of the buffers is 9.54 mW from a supply voltage of 1.8 V. The measured phase noise of the divider is -141.3 dBc/Hz at 1-MHz offset when the input referred signal with a phase noise of -132.8 dBc/Hz at 1-MHz offset from 24 GHz. The phase-noise difference of 8.5 dB is close to the theoretical value of 9.5 dB for division-by-3. The output power of the divider is more than -11 dBm over the whole locking range.

K

We have extensively measured and analyzed the current mismatch of a small-size n-channel MOS transistor of 2 /spl mu/m/spl times/2 /spl mu/m operated in weak inversion with its p-well-to-n/sup +/-source junction forward and reverse biased. The case of slightly forward biasing the well-to-source junction represents the action of a gated lateral bipolar transistor in low level injection. The measured dependencies of the mismatch in weak inversion on the back-gate forward and reverse biases have been successfully reproduced by a new simple statistical model. From the experimental data, we suggest that i) subthreshold circuits should be carefully designed for suppression of mismatch arising from back-gate reverse bias, and ii) a gated lateral bipolar action in low level injection may be utilized as a new method of improving the transistor matching.

-Band Divide-by-3 Injection-Locked Frequency Divider With Floating-Source Differential Injector

This brief presents the integration of an 8-GHz voltage-controlled oscillator (VCO) and a frequency tripler for 24-GHz local oscillator generation. By stacking the VCO and the tripler with a current-reused topology, the power consumption of this integration can be saved. The proposed circuit with a total chip area of 0.7 mm × 0.8 mm is implemented in a 0.18-μm CMOS process. As the tuning voltage increases from 0 to 2 V, the measured frequency tuning range (FTR) of the VCO is from 7.06 to 8.33 GHz. The final resulting output frequency from the tripler ranges from 21.18 to 24.98 GHz (16.5% FTR). The core circuit totally consumes 5 mA from a 1.8-V supply voltage. The measured phase noises at the VCO and frequency tripler outputs are -113.76 and -105.1 dBc/Hz at 1-MHz offset frequency, respectively, when Vtune is 0 V. The best evaluated figure of merit with tuning is -187.2 dBc/Hz. This integration of a VCO and a frequency tripler exhibits a high potential for the use in low-power 24-GHz phase-locked loops.

Dependence of current match on back-gate bias in weakly inverted MOS transistors and its modeling

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the FOMT.

Integration of Current-Reused VCO and Frequency Tripler for 24-GHz Low-Power Phase-Locked Loop Applications

Abstract The I–V characteristics of a gated lateral bipolar transistor in an n-MOSFET structure have been measured. The measured collector current has exhibited two distinct components: (i) the gate-controlled collector current due to the modulation of the surface space-charge region; and (ii) the pure lateral bipolar transistor collector current which is independent of the gate bias applied. These two components have been separated experimentally and have been reproduced by analytic model expressions. The work is useful not only for understanding the hybrid-mode operation but also for designing appropriately the gated lateral bipolar transistors.

A Switched Inductor Topology Using a Switchable Artificial Grounded Metal Guard Ring for Wide-FTR MMW VCO Applications

This work presents a 27-GHz low phase-noise standing-wave voltage controlled oscillator (VCO) design with the folded microstrip line structure over floating metal strips. Because the floating metal strips serve to retard the wave, the length of microstrip line (and thus the overall layout area) can be further reduced at a given frequency. Meanwhile, the floating metal strips reduce the substrate effect and improve the Q-factor of the microstrip line. The measurement results exhibit a tuning range from 26.26 GHz to 26.80 (27.55) GHz with the tuning voltage rising from 0.1 V to 1.8 (3.3) V. The measured phase-noise levels are around −115 dBc/Hz and −134 dBc/Hz at 1-MHz and 10-MHz offset, respectively. The DC power consumption of the oscillator core is 17.7 mW at the supply voltage of 1.8 V. The figure of merits (FOM) of this VCO is −191 dB.

Empirical modeling for gate-controlled collector current of lateral bipolar transistors in an n-MOSFET structure

This paper presents a 60GHz high-isolation CMOS single-pole double-throw (SPDT) transmitter/receiver (T/R) switch fabricated with TSMC standard 90-nm 1P9M CMOS technology. A low insertion loss and high linearity are achieved by using the body-floating technique. The leakage cancellation technique is used to increase the isolation between the transmitter and receiver ports. The top metal (M9) is mainly adopted for designing signal paths and the microstrip-line matching elements. In order to minimize the substrate loss, the first metal (M1) as the ground plane is used in this design. The measured results show the insertion loss from the transmitter port to the antenna port is less than 3.5 dB, and the isolation between the transmitter and receiver ports is higher than 28 dB from 57 to 64GHz. At the center frequency of 60GHz, the port isolation is higher than 34 dB and the input 1-dB compression point (IP1dB) is +6.9 dBm.