U. Konig

High hole mobility in Si0.17Ge0.83 channel metal–oxide–semiconductor field-effect transistors grown by plasma-enhanced chemical vapor deposition

We report on effective hole mobility in SiGe-based metal–oxide–semiconductor (MOS) field-effect transistors grown by low-energy plasma-enhanced chemical vapor deposition. The heterostructure layer stack consists of a strained Si0.17Ge0.83 alloy channel on a thick compositionally-graded Si0.52Ge0.48 buffer. Structural assessment was done by high resolution x-ray diffraction. Maximum effective hole mobilities of 760 and 4400 cm2/Vs have been measured at 300 and 77 K, respectively. These values exceed the hole mobility in a conventional Si p-MOS device by a factor of 4 and reach the mobility data of conventional Si n-MOS transistors.

p-type Ge-channel MODFETs with high transconductance grown on Si substrates

Modulation-doped FET (MODFET) structures with hole channels consisting of pure Ge were grown by molecular beam epitaxy (MBE) on Si substrates. To overcome the relatively large lattice mismatch, between Si and Ge, a relaxed Si/sub 1-x/Ge/sub x /buffer layer with linearly graded Ge concentration and a final x value of around 70% was grown first. Hall mobilities of up to 1300 cm/sup 2//V-s at room temperature and 14000 cm/sup 2//V-s at 77 K were measured. Devices with and without gate recess were fabricated, which result in enhancement- and depletion-type FETs. Maximum extrinsic transconductances of 125 and 290 mS/mm at room temperature and 77 K, respectively, were found for gate lengths L/sub G/ around 1.2 mu m.<<ETX>>

MBE-grown Si/SiGe HBTs with high beta , f/sub T/, and f/sub max/

Si/SiGe heterojunction bipolar transistors (HBTs) were fabricated by growing the complete layer structure with molecular beam epitaxy (MBE). The typical base doping of 2*10/sup 19/ cm/sup -3/ largely exceeded the emitter impurity level and led to sheet resistances of about 1 k Omega / Square Operator . The devices exhibited a 500-V Early voltage and a maximum room-temperature current gain of 550, rising to 13000 at 77 K. Devices built on buried-layer substrates had an f/sub max/ of 40 GHz. The transit frequency reached 42 GHz.<<ETX>>

SiGe HBTs and HFETs

Abstract SiGe is just on an upswing. Attractive potentials can be foreseen and outstanding performance was even demonstrated, e.g. high frequencies above 100 GHz, low noise below 0.5 dB at 2 GHz, high transconductances around 400 mS/mm. A further driving force for the growing engagement with SiGe is its basic compatibility to standard Si-technology. Though most of the results stem from discrete devices SiGe is already going to be produced. The first devices will be SiGe-heterobipolar transistors (HBT). Targeted applications are converters or mobile communication systems. The status of our devices is reviewed here. In long term the SiGe hetero fieldeffect transistor (HFET) will become another candidate creating a new advanced generation in mainstream CMOS, s.c. SiGe Hetero CMOS (HCMOS). Our status of SiGe HFETs and its potential for HCMOS is presented also.

SiGe-based FETs: buffer issues and device results

Abstract SiGe quantum well structures gain increasing interest in the Si technology. The preparation of a Si channel or a Ge-rich or even a pure Ge channel with a respective two-dimensional carrier gas opens the attractive possibility to fabricate high performance n - or p -type field effect transistors. For both device types, a virtual substrate surface is required which is created by a strain relieved buffer layer grown on a Si standard wafer. The paper reviews various approaches of SiGe buffers including special attempts to reduce the thickness and to improve the quality. N - and p -type modulation-doped field-effect transistors are presented which show comparably good device characteristics and cut-off frequencies in the range of 100–120 GHz.

Design rules for n-type SiGe hetero FETs

Simulations of n-type SiGe Hetero field effect transistors (HFETs) were performed to improve their vertical and lateral design. Position and intensity of the doping was changed at the front side, backside and even inside the 2DEG Si-channel. Sheet carrier concentrations up to 4 × 1012cm−2 were envisaged. Schottky and MOS versions were simulated. A novel structure with a p-type cap is proposed that reduces the threshold in a MOS gated HFET. The effect of the nm-spacer between doping and 2 DEG is studied. Effects of gate lengths LG and source-gate distance LSG were simulated for depletion or enhancement mode. Transconductances up to 1000 mS mn−1 should be possible in selfaligned layouts with LG < 0.1 μm. The gate length dependence of frequencies with and without velocity overshoot point to values distinctly above 200 GHz. Simulated gate delays of NOR and NAND n-HFET circuits in a relaxed design (LG = 0.8 μm) promise data around 500 ps, more than double as fast as for respective standard CMOS.

Si/SiGe n-MODFETs on thin SiGe virtual substrates prepared by means of He implantation

Si/SiGe n-type modulation-doped field-effect transistors grown on a very thin strain-relieved Si/sub 0.69/Ge/sub 0.31/ buffer on top of a Si(100) substrate were fabricated and characterized. This novel type of virtual substrate has been created by means of a high dose He ion implantation localized beneath a 95-nm-thick pseudomorphic SiGe layer on Si followed by a strain relaxing annealing step at 850/spl deg/C. The layers were grown by molecular beam epitaxy. Electron mobilities of 1415 cm/sup 2//Vs and 5270 cm/sup 2//Vs were measured at room temperature and 77 K, respectively, at a sheet carrier density of about 3/spl times/10/sup 12//cm/sup 2/. The fabricated transistors with Pt-Schottky gates showed good dc characteristics with a drain current of 330 mA/mm and a transconductance of 200 mS/mm. Cutoff frequencies of f/sub t/=49 GHz and f/sub max/=95 GHz at 100 nm gate length were obtained which are quite close to the figures of merit of a control sample grown on a conventional, thick Si/sub 0.7/Ge/sub 0.3/ buffer.

Mesa and planar SiGe-HBTs on MBE-wafers

SiGe-HBTs have the potential for outstanding analog and digital or mixed-signal high frequency circuits widely based on standard Si technology. Here we review on MBE grown transistors and circuits. Processes and results of a research-like SiGe HBT and two possible production relevant HBT versions are presented. The high frequency results with fmax and fT up to 120 GHz and a minimum noise figure of 0.9 dB at 10 GHz demonstrate the advantage of using MBE samples with steep and high base doping and high germanium contents. A comparison to the concept of reported low doped, low germanium and triangular profiled SiGe base layers, realized by UHV-CVD, is given. In addition, some circuit demonstrators of SiGe-ICs will be presented.

n- and p-Type SiGe HFETs and circuits

n- and p-Type SiGe HFETs exhibit advanced performance especially favourable for RF-applications. Due to strained channels high carrier mobilities at room temperature (2700 and 1870 cm2/V s) and large sheet carrier densities (ns=6.4×1012 cm×2 and ps=2.1×1012 cm×2) have been achieved. For the n-MODFET (LG>=150 nm) tensile strained Si channels embedded in SiGe layers lead to a maximal gme of 476 mS/mm and to cut-off frequencies of ft=43 GHz and fmax=92 GHz. The best results for p-type HFETs were attained for a pure Ge channel MODFET with ft=32 GHz and fmax=85 GHz. Analog and digital circuit realizations for the n-MODFET resulted in a transimpedance amplifier yielding a Z21 of 56 dB Ω at a bandwidth of 1.8 GHz and an inverter with a gate delay of 25 ps.

High performance 100 nm T-gate strained Si/Si0.6Ge0.4 n-MODFET

Abstract 100 nm T-gate strained Si/Si 0.6 Ge 0.4 n-MODFETs have reached new record cut-off frequency f T of 74 GHz (105 GHz), with maximum oscillation frequency f max of 107 GHz (170 GHz) at temperatures 300 K (50 K). Moreover they show a low noise figure NF min of 0.4 dB and noise resistance R n of 52 Ω at 2.5 GHz and 300 K. The dependence of electric parameters and RF performances of the device on biases and temperature is presented. Experimental results are compared with physical simulations at short gate lengths to analyze carrier transport and further device optimization.