Ugur Sezer

An integer linear programming based approach for parallelizing applications in on-chip multiprocessors

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a parallelization strategy based on integer linear programming. Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each nest based on the objective function and additional compilation constraints provided by the user. Our initial experience with this strategy shows that it is very successful in optimizing array-intensive applications on on chip multiprocessors under energy and performance constraints.

Exploiting scratch-pad memory using Presburger formulas

Effective utilization of on-chip storage space is important from both performance (execution cycles) and memory system energy consumptions perspectives. While on-chip cache memories have been widely used in the past, several factors, including lack of data access time predictability and limited effectiveness of compiler optimizations, indicate that they may not be the best candidate for portable/embedded devices. This paper presents a compiler-directed on-chip scratch-pad memory (software-managed on-chip memory) management strategy for data accesses. Our strategy is oriented towards minimizing the number of data transfers between off-chip memory and the scratch-pad memory, thereby exploiting reuse for the data residing in the scratch-pad memory. We report experimental data from our implementation showing the usefulness of our technique.

Improving memory energy using access pattern classification

In this paper, we propose a data-driven strategy to optimize the memory energy consumption in a banked memory system. Our compiler-based strategy modifies the original execution order of loop iterations in array-dominated applications to increase the length of the time period(s) in which memory banks axe idle (i.e., not accessed by any loop iteration). To achieve this it first classifies loop iterations according to their bank access patterns and then, with the help of a polyhedral tool, tries to bring the iterations with similar bank access patterns close together. Increasing the idle periods of memory banks brings two major benefits; first, it allows us to place more memory banks into low-power operating modes, and second, it enables us to use a more aggressive (i.e., more energy saving) operating mode for a given bank. Our strategy has been evaluated using seven array-dominated applications on both a cacheless system and a system with cache memory. Our results indicate that the strategy is very successful in reducing the memory system energy, and improves the memory energy by as much as 34% on the average.

Configuration-sensitive process scheduling for FPGA-based computing platforms

Reconfigurable computing has become an important part of research in software systems and computer architecture. While prior research on reconfigurable computing have addressed architectural and compilation/programming aspects to some extent, there is still not much consensus on what kind of operating system (OS) support should be provided. In this paper, we focus on OS process scheduler, and demonstrate how it can be customized considering the needs of reconfigurable hardware. Our process scheduler is configuration sensitive, that is, it reuses the current FPGA configuration as much as possible. Our extensive experimental results show that the proposed scheduler is superior to classical scheduling algorithms such first-come-first-serve (FCFS) and shortest job first (SJF).

Optimizing array-intensive applications for on-chip multiprocessors

With energy consumption becoming one of the first-class optimization parameters in computer system design, compilation techniques that consider performance and energy simultaneously are expected to play a central role. In particular, compiling a given application code under performance and energy constraints is becoming an important problem. In this paper, we focus on an on-chip multiprocessor architecture and present a set of code optimization strategies. We first evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using a different number of processors if doing so is beneficial) and measure the potential energy savings when unused processors during execution of a nested loop are shut down (i.e., placed into a power-down or sleep state). Our results show that shutting down unused processors can lead to as much as 67 percent energy savings at the expense of up to 17 percent performance loss in a set of array-intensive applications. To eliminate this performance penalty, we also discuss and evaluate a processor preactivation strategy based on compile-time analysis of nested loops. Based on our experiments, we conclude that an adaptive loop parallelization strategy combined with idle processor shut down and preactivation can be very effective in reducing energy consumption without increasing execution time. We then generalize our strategy and present an application parallelization strategy based on integer linear programming (ILP). Given an array-intensive application, our optimization strategy determines the number of processors to be used in executing each loop nest based on the objective function and additional compilation constraints provided by the user/programmer. Our initial experience with this constraint-based optimization strategy shows that it is very successful in optimizing array-intensive applications on on-chip multiprocessors under multiple energy and performance constraints.

Access pattern restructuring for memory energy

Improving memory energy consumption of programs that manipulate arrays is an important problem as these codes spend large amounts of energy in accessing off-chip memory. We propose a data-driven strategy to optimize the memory energy consumption in a banked memory system. Our compiler-based strategy modifies the original execution order of loop iterations in array-dominated applications to increase the length of the time period(s) in which memory banks are idle (i.e., not accessed by any loop iteration). To achieve this, it first classifies loop iterations according to their bank accesses patterns and then, with the help of a polyhedral tool, tries to bring the iterations with similar bank access patterns close together. Increasing the idle periods of memory banks brings two major benefits: first, it allows us to place more memory banks into low-power operating modes and, second, it enables us to use a more aggressive (i.e., more energy saving) operating mode (hence, saving more energy) for a given bank (instead of a less aggressive mode). The proposed strategy can reduce memory energy consumption in both sequential and parallel applications. Our strategy has been implemented in an experimental compiler using a polyhedral tool and evaluated using nine array-dominated applications on both a cacheless system and a system with cache memory. Our experimental results indicate that the proposed strategy is very successful in reducing the memory system energy and improves the memory energy by as much as 36.8 percent over a strategy that uses low-power modes without optimizing data access pattern. Our results also show that optimizations that target reducing off-chip memory energy can generate very different results from those that target at improving only cache locality.

Improving off-chip memory energy behavior in a multi-processor, multi-bank environment

Many embedded/portable applications from image and video processing domains are characterized by spending a large fraction of their energy in executing load/store instructions that access off-chip memory. Although most performance-oriented locality optimization techniques reduce the number of memory instructions and, consequently, improve memory energy consumption, we also need to consider energy-oriented approaches if we are to improve energy behavior further. Our focus in this paper is on a system with multiple homogeneous processors and a multi-bank memory architecture that process large arrays of signals. To reduce energy consumption in such a system, we use a compiler-based approach which exploits low-power operating modes. In such an architecture, one of the major problems is to address the conflicting requirements of maximizing parallelism and reducing energy consumption. This conflict arises because maximizing parallelism requires independent concurrent accesses to different memory banks, whereas reducing energy consumption implies limiting the accesses at a given period of time to a small set of memory banks (so that the remaining banks can be placed into a low-power operating mode). Our approach consists of three complementary steps, namely, parallel access pattern detection, array allocation across memory banks, and data layout transformations. Our preliminary results indicate that our approach leads to significant off-chip memory energy savings without sacrificing the available parallelism.

Compiler-directed management of instruction accesses

We present a compiler-oriented strategy to reduce the memory system energy consumption due to instruction accesses and increase performance by exploiting scratch pad memories. Scratch pad memories (SPMs) are alternatives to conventional cache memories in embedded computing. These small on-chip memories, like caches, provide fast and low-power access to data and instructions; but, they differ from caches in that their contents are managed by software instead of hardware. Our compiler framework keeps the most frequently used instructions in SPM and dynamically changes the contents of the SPM as the (instruction) working set of the application changes.

Reliability-conscious process scheduling under performance constraints in FPGA-based embedded systems

This paper proposes, for the FPGA-based embedded systems, a reliability-aware process scheduling strategy that operates under performance bounds. A unique characteristic of the proposed approach is that it employs multiple implementations (also called versions) of a given process; each version differs from the other implementations (of the same process) from the viewpoint of reliability, performance, power, or area metrics. Our scheme, which can work under a base scheduler or independently, tries to use the most reliable version for each process, restricted only by the performance bound specified. We implemented this scheme and simulated it using a custom simulator.

Array Composition and Decomposition for Optimizing Embedded Applications

Optimizing array accesses is extremely critical in embedded computingas many embedded applications make use of arrays (in formof images, video frames, etc). Previous research considered bothloop and data transformations for improving array accesses. However,data transformations considered were mostly limited to lineardata transformations and array interleaving. In this paper, we introducetwo data transformations: array decomposition (breaking upa large array into multiple smaller arrays) and array composition(combining multiple small arrays into a single large array). Thispaper discusses that it is feasible to implement these optimizationswithin an optimizing compiler.