Ulf Pillkahn

Structural test in a board self test environment

In this paper, a novel technique for the verification of board level connections on PCBs is presented. The time domain method is used to identify whether a pin connection is faulty or not. The test pulse and evaluation circuitry are part of the chip. Although the chip size increases slightly, the method is highly efficient. No ATE is necessary to carry out the test and since only the physical behaviour of the connection from the internal driver via pin to board is examined, no test vectors are needed. The test time and the test preparation time are lower compared with conventional test methods.

Zukunftsbetrachtungen und Prognosen im Unternehmensumfeld

Im Allgemeinen geht man davon aus, dass die Zukunft nicht vorhersehbar ist. Schon falsch. Die vielen Aussagen uber Zukunftiges zeigen ja genau das Gegenteil. Die Gute der reichlich publizierten „Vorhersagen“ ist das eigentliche Problem. Viele fuhlen sich berufen, es halt auch nur wenige davon ab, zahlreiche Positionen „wie es werden wird“ zu veroffentlichen. Das gilt prinzipiell genauso auch fur Zukunftsbetrachtungen im Unternehmensumfeld und es gibt noch ein paar Besonderheiten.

Evaluation of interconnects with TDR (poster paper)

In this paper, a novel technique is presented for the verification of board level connections on PCBs. The time domain reflectometry (TDR) method is used to identify whether a pin connection is faulty or not. The test pulse and evaluation circuitry is part of the chip. Although the chip size increases slightly, the method is highly efficient. No Automatic Test Equipment (ATE) is necessary to carry out the test and since only the physical behaviour of the connection from the internal driver via pin to board is examined, no test vectors are needed. The test time and the test preparation time are lower compared with conventional test methods. Introduction The proposed method is intended for total selftest applications without external test equipment. Common test approaches compare testpatterns on the send and receive side and require thus a substantial amount of memory, circuit logic and computer power. With this method, the test result can be determined immediately after the test. The test circuitry can be minimized to chip level size and is ideal for a selftest strategy. Test Principle The connection under test is considered as a transmission line and has to be stimulated such, that the response can be evaluated and accessed on the internal test observation circuit (Fig.: 1).

Evaluation of interconnects with TDR

Summary form only given. In this paper, a novel technique is presented for the verification of board level connections on PCBs. The time domain reflectometry (TDR) method is used to identify whether a pin connection is faulty or not. The test pulse-and evaluation circuitry is part of the chip. Although the chip size increases slightly, the method is highly efficient. No Automatic Test Equipment (ATE) is necessary to carry out the test and since only the physical behaviour of the connection from the internal driver via pin to board is examined, no test vectors are needed. The test time and the test preparation time are lower compared with conventional test methods.