Uwe Kirchner

Performance of a 650V SiC Diode with Reduced Chip Thickness

A significant performance gain of 650V SiC diodes is possible by reducing the wafer thickness from the standard thickness of 350 µm to < 150 µm. Not only the differential resistance of the diodes but also the Rth benefit from this chip thickness reduction. As consequence a further chip size reduction with accompanying capacitive charge reduction leads to a device with improved efficiency in PFC applications under both high load and low load conditions.

650V SiC JFET for High Efficiency Applications

This paper presents for the first time a 650V SiC JFET switch. Although this application class is highly competitive and occupied by Silicon devices the characterization data show unique features which make the SiC switch an outstanding option for future system integration.