Uwe Meyer-Baese

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

Robust Bioinspired Architecture for Optical-Flow Computation

Motion estimation from image sequences, called optical flow, has been deeply analyzed by the scientific community. Despite the number of different models and algorithms, none of them covers all problems associated with real-world processing. This paper presents a novel customizable architecture of a neuromorphic robust optical flow (multichannel gradient model) based on reconfigurable hardware with the properties of the cortical motion pathway, thus obtaining a useful framework for building future complex bioinspired real-time systems with high computational complexity. The presented architecture is customizable and adaptable, while emulating several neuromorphic properties, such as the use of several information channels of small bit width, which is the nature of the brain. This paper includes the resource usage and performance data, as well as a comparison with other systems. This hardware platform has many application fields in difficult environments due to its bioinspired nature and robustness properties, and it can be used as starting point in more complex systems.

FAST RNS FPL-BASED COMMUNICATIONS RECEIVER DESIGN AND IMPLEMENTATION

Currently, several design barriers inhibit the implementation of high-precision digital signal processing (DSP) systems with field programmable logic (FPL) devices. A new demonstration of the synergy between the residue number system (RNS) and FPL technology is presented in this paper. The quantifiable benefits of this approach are studied in the context of a high-end communications digital receiver. A new RNS-based direct digital synthesizer (DDS) that does not need a scaler circuit is introduced. The programmable decimation FIR filter is based on the arithmetic benefits associated with Galois fields and supports tuning the IF frequency as well as its bandwidth. Results show the proposed methodology requires fewer resources than classical designs, while throughput advantage is about 65%.

Pipelined Hogenauer CIC filters using field-programmable logic and residue number system

Field-programmable logic (FPL) is on the verge of revolutionizing digital signal processing (DSP) in the manner that programmable DSP microprocessors did nearly two decades ago. While FPL densities and performance have steadily improved to the point where some DSP solutions can be integrated into a single FPL chip, they still have limited use in high-precision high-bandwidth applications. It is shown that in such cases, the residue number system (RNS) can be an enabling technology. The design of a high-decimation rate digital filter is presented which demonstrates the RNS-FPL synergy.

FPGA-Based Multimodal Embedded Sensor System Integrating Low- and Mid-Level Vision

Motion estimation is a low-level vision task that is especially relevant due to its wide range of applications in the real world. Many of the best motion estimation algorithms include some of the features that are found in mammalians, which would demand huge computational resources and therefore are not usually available in real-time. In this paper we present a novel bioinspired sensor based on the synergy between optical flow and orthogonal variant moments. The bioinspired sensor has been designed for Very Large Scale Integration (VLSI) using properties of the mammalian cortical motion pathway. This sensor combines low-level primitives (optical flow and image moments) in order to produce a mid-level vision abstraction layer. The results are described trough experiments showing the validity of the proposed system and an analysis of the computational resources and performance of the applied algorithms.

A low cost matching motion estimation sensor based on the NIOS II microprocessor.

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented here together with an extensive analysis of the resources needed and the throughput obtained. The developed low-cost system is practical for real-time throughput and reduced power consumption and is useful in robotic applications, such as tracking, navigation using an unmanned vehicle, or as part of a more complex system.

Optimization of high speed pipelining in FPGA-based FIR filter design using genetic algorithm

This paper compares FPGA-based full pipelined multiplierless FIR filter design options. Comparison of Distributed Arithmetic (DA), Common Sub-Expression (CSE) sharing and n-dimensional Reduced Adder Graph (RAG-n) multiplierless filter design methods in term of size, speed, and A*T product are provided. Since DA designs are table-based and CSE/RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Superior results of a genetic algorithm based optimization of pipeline registers and non-output fundamental coefficients are shown. FIR filters (posted as open source by Kastner et al.) for filters in the length from 6 to 151 coefficients are used.

A Comparison of Pipelined RAG-n and DA FPGA-based Multiplierless Filters

The paper starts with an overview of distributed arithmetic (DA) and n-dimensional reduced adder graph (RAG-n) multiplierless filter design methods. Since DA designs are table-based and RAG-n designs are adder-based, FPGA synthesis design data are used for a realistic comparison. Benchmark FIR filters (Goodman and Carey, 1977) of length 11 to 63 are compiled. For a wide set of realistic design examples, it will be shown that pipelined RAG-n designs achieve on average a gain of 71% in area, equivalent performance in speed, and a 56% improvement in cost compared with DA-based designs

Discrete wavelet transform FPGA design using MatLab/Simulink

Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of the engineering shlls ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink based design flow. This not only allows the over 1 million MatLab users to design FPGAs but also to by-pass the hardware design engineer leading to a significant reduction in development time. Critical however with this design flow are: (1) quality-of-results, (2) sophistication of Simulink block library, (3) compile time, (4) cost and availability of development boards, and (5) cost, functionality, and ease-of-use of the FPGA vendor provided design tools.

Multiple constant multiplication with ternary adders

The scaling operation, i. e., the multiplication with a single constant is a frequently used operation in many kinds of numeric algorithms. The multiple constant multiplication (MCM) is a generalization where a variable is multiplied by several constants. This kind of operation is heavily used, e. g., in digital filters or discrete transforms. It was shown in recent work that small, fast and power efficient MCM implementations can be realized by using the fast carry chains of FPGAs rather than wasting specialized embedded multipliers. However, in the work so far, only common two-input adders were used. As FPGAs today support ternary adders, i. e., adders with three inputs, this work investigates the optimization of pipelined MCM circuits which include ternary adders. It is shown experimentally that 27% less operations are needed on average by using ternary adders, resulting in 15% slice (Xilinx) and 10% ALM (Altera) reductions, respectively.