V. Bonaiuto

6/spl times/6 DPCNN: a programmable mixed analogue-digital chip for cellular neural networks

The implementation of a versatile VLSI chip represents an important step to develop cellular neural networks (CNN). In this paper a VLSI realization of the multi-chip oriented, 6/spl times/6 digitally programmable cellular neural network (6/spl times/6 DPCNN) chip, is presented. This chip covers most of the available one-neighbourhood templates for image processing applications. Moreover, it can be easily interconnected to others to form very large CNN arrays.

A 6 × 6 Cells Interconnection-OrientedProgrammable Chip for CNN

The implementation of a versatile VLSI chip certainly represents an important step to improve the research on Cellular Neural Networks. In this paper a VLSI realization of the multi-chip oriented, the 6 × 6 Digitally Programmable Cellular Neural Network (6 × 6 DPCNN) chip, will be presented. This chip covers most of the available one-neighbourhood templates for image processing applications. Moreover, it can be easily interconnected to others to carry out very large CNN arrays. The designs and some measured results of a single chip and a multi-chip board (the 720 DPCNN System) will be shown.

A fully digitally programmable CNN chip

The successful development of cellular neural networks is dependent on hardware implementation. This letter presents a VLSI implementation of a multichip-oriented, fully programmable, 3/spl times/3 digitally programmable cellular neural network (DPCNN). This chip covers most of the available one-neighborhood templates for image processing applications. Moreover, it can be easily interconnected to others to carry out very large CNN arrays. >

High performance digitally programmable CNN chip with discrete templates

In this paper a high performance VLSI implementation of a 3/spl times/3 Digitally Programmable Cellular Neural Network with discrete templates is presented. This chip, manufactured and successfully tested, gives an efficient solution to the hardware implementation of the Cellular Neural Networks. Moreover this chip can be connected to others to carry out very large CNN arrays. This implementation covers the 66% of the available one-neighborhood fixed templates for image processing applications.<<ETX>>

A Dedicated Multi-Chip Programmable System for Cellular Neural Networks

Cellular Neural Networks (CNNs) represent a remarkable improvement in the hardware implementation of Artificial Neural Networks (ANNs). In fact, their regular structure and their local connectivity feature contribute to render this class of neural networks especially appealing for VLSI implementations. CNNs are widely applied in several fields, including image processing and pattern recognition. In this research, the authors already presented two fully digitally programmable CNN chips with 3×3 (3×3DPCNN chip) and 6×6 cells (6×6DPCNN chip) respectively. In this paper, a system with twenty of the latter chips will be presented. The main features of this electronic system consist of the full digital programmability of the templates, the digital input/output for logic operations, the analog outputs for dynamic analysis and the implementation of space-variant as well as space-invariant CNNs.

A 720 cells interconnection-oriented system for cellular neural networks

Cellular Neural Networks (CNNs) represent a remarkable improvement in hardware implementation of Artificial Neural Networks. In fact, their regular structure and their local connectivity feature make this class of neural networks really appealing for VLSI implementations. The CNN are widely used in several application fields, such as image processing and pattern recognition. In this research area, the authors presented a fully digitally programmable CNN chip with 6/spl times/6 cells (6/spl times/6DPCNN chip). In this paper, a system with twenty of these chips will be presented. This system is made up of twenty boards with one 6/spl times/6DPCNN chip each. Its main features are: fully programmability of the templates; digital input/output for logic operation; analog outputs for dynamic analysis; implementation of space-variant as well as space-invariant CNN.

DPCNN: a modular chip for large CNN arrays

The VLSI implementation of Cellular Neural Networks is a relevant task which is very important for the future development of neural networks. In this paper a a modular VLSI implementation of a 3/spl times/3 Digitally Programmable Cellular Neural Networks is presented. This chip is the first successfully tested fully programmable Cellular Neural Network hardware implementation. It covers most of the available one-neighborhood templates for image processing applications. Moreover, it has been designed to be easily interconnected to others to give very large CNN arrays.

Design of a dedicated CNN chip for autonomous robot navigation

Obstacle avoidance is the main issue in autonomous robotics. It requires a three-dimensional effective environment sensing in real time. Among the others, the stereo vision approach to environmental information extraction seems to be very appealing, even if it leads an extremely high computational cost. However, a high performance implementation of this algorithm on a cellular neural network is able to overcome these difficulties. In the paper, the design of a CNN chip well suited for this algorithm is presented. This chip, performing a real time processing of the stereo vision data, will improve the cruising speed of a robotic platform.

A 3 × 3 digitally programmable CNN chip

In this paper a VLSI implementation of a 3 × 3 cell digitally programmable cellular neural networks (CNN) with discrete templates is presented. This chip is the first successfully tested, multichip-oriented CNN chip. In fact, this chip has been designed to be easily interconnected to others to carry out very large CNN arrays. This feature has been verified in a two-chip prototype board. The fully programmable capability covers most of the available one-neighbourhood fixed templates.

Hardware implementation of a CNN for analog simulation of reaction-diffusion equations

In this paper the hardware implementation is discussed of a cellular nonlinear network (CNN) for analog simulation of reaction-diffusion partial differential equations. The elementary cell consists of the classic nonlinear circuit typical in these CNNs, except for the characteristic of the nonlinear resistor; that is chosen to be non-monotone. The control laws describing the contribution of the neighbor cells depend both on the currents and the voltages of the capacitors.