V. González

Control de las cifras de presión arterial en los pacientes hipertensos con hipertrofia ventricular: estudio VIIDA

Introduction and objectives. The aims were to determine the effectiveness of blood pressure (BP) control in hypertensive patients with left ventricular hypertrophy (LVH), as detected by ECG, and to identify the variables associated with poor control, particularly in diabetics. Methods. The study included hypertensive patients with ECG evidence of LVH who attended cardiology outpatient clinics between April 2003 and November 2004. Patient characteristics and clinical variables were recorded on admission to the study. Results. Of the 16 123 patients included, 4037 (25.04%) had LVH at presentation. Some 58.1% of these latter patients had a history of cardiovascular disease. Only 8.1% of diabetic patients had BP values below 130/80 mm Hg, whereas 22.4% of nondiabetic patients were well-controlled. Multivariate analysis showed that the only independent predictors of poor BP control were diabetes (odds ratio [OR]= 3.62, 95% confidence interval, [CI] 2.7‐4.7), female sex (OR= 1.18, 95% CI, 1.02‐1.33), increased voltage recording in lead V5 (OR= 1.027 per mm, 95% CI, 1.01‐1.03), and body mass index (OR= 1.03, 95% CI, 1.00‐1.05), whereas a history of cardiovascular disease was associated with good BP control (OR= 0.57, 95% CI, 0.48‐0.70). Conclusions. The prevalence of LVH, as identified by ECG, was high in hypertensive patients attending cardiology outpatient clinics, and comorbid conditions were common. Control of BP was suboptimal, particularly in diabetic patients, fewer than 10% of whom were wellcontrolled. Finally, BP control in patients with LVH was influenced by sex, body mass index, and a history of cardiovascular disease.

Development of the Optical Multiplexer Board Prototype for Data Acquisition in the TileCal System

This paper describes the development of the optical multiplexer board (OMB), also known as PreROD board, for the TileCal readout system in the ATLAS experiment. The aim of this board is to overcome the problems that may arise in the integrity of data due to radiation effects. The solution adopted has been to add redundancy to data transmission and so two optical fibers with the same data come out from the detector front end boards. The OMB has to decide in real time which fiber, eventually, carries data with no errors switching it to the output link connected to the read out driver (ROD) motherboard where data processing takes place. Besides, the board may be also used as a data injector for testing purposes of the ROD motherboard. The paper describes the design and tests of the first prototype, implemented as a 6U VME64x slave module, including both hardware aspects, focusing on signal integrity problems, and firmware aspects, dealing with the cyclic redundancy code algorithms used to check data consistency used to make the decision

ATLAS TileCal read out driver production

The production tests of the 38 ATLAS TileCal Read Out Drivers (RODs) are presented in this paper. The hardware specifications and firmware functionality of the RODs modules, the test-bench and the test procedure to qualify the boards are described. Finally the performance results, the temperature studies and high rate tests are shown and discussed.

Performance of the Fully Digital FPGA-Based Front-End Electronics for the GALILEO Array

In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. This work presents the first results of the digital FEE system coupled with a GALILEO germanium detector, which has demonstrated the capability to achieve an energy resolution of 1.530/00 at an energy of 1.33 MeV, similar to the one obtained with a conventional analog system. While keeping a good performance in terms of energy resolution, digital electronics will allow to instrument the full GALILEO array with a versatile system with high integration and low power consumption and costs.

DSP Online Algorithms for the ATLAS TileCal Read-Out Drivers

TileCal is the hadronic tile calorimeter of the ATLAS experiment at LHC/CERN. The central element of the back-end system of the TileCal detector is the read-out driver (ROD).The main components of the TileCal ROD are the digital signal processors (DSPs) placed on the processing unit (PU) daughterboards. This paper presents a detailed description of the code developed for the DSPs. The code is divided into two different parts: the first part contains the core functionalities and the second part the reconstruction algorithms. The core acts as an operating system and controls configuration, data reception and transmission and synchronization between front-end data and the timing, trigger and control (TTC) information. The reconstruction algorithms implemented on the DSP are the optimal filtering (OF), muon tagging (MTag) and missing ET calculation. The OF algorithm reconstructs the deposited energy and the arrival time of the signal for every calorimeter channel within a front-end module. This reconstructed energy is used by the MTag algorithm to tag low transverse momentum muons that may escape the ATLAS muon spectrometer level 1 trigger whereas the missing ET algorithm computes the total transverse energy and the projection on X and Y axis for the entire module that will be used by the level 2 trigger system.

Algorithms for the ROD DSP of the ATLAS hadronic Tile Calorimeter

In this paper we present the performance of two algorithms currently running in the Tile Calorimeter Read-Out Driver boards for the commissioning of ATLAS. The first algorithm presented is the so called Optimal Filtering. It reconstructs the deposited energy in the Tile Calorimeter and the arrival time of the data. The second algorithm is the MTag which tags low transverse momentum muons that may escape the ATLAS muon spectrometer first level trigger. Comparisons between online (inside the Read-Out Drivers) and offline implementations are done with an agreement around 99% for the reconstruction of the amplitude using the Optimal Filtering algorithm and a coincidende of 93% between the offline and online tagged muons for the MTag algorithm. The processing time is measured for both algorithms running together with a resulting time of 59.2 μs which, although above the 10 μs of the first level trigger, it fulfills the requirements of the commissioning trigger ( ~ 1 Hz). We expect further optimizations of the algorithms which will reduce their processing time below 10 μs.

A VLSI for deskewing and fault tolerance in LVDS links

The device presented at this work is a switch implemented in a 0.35 mum CMOS process for compensating the skew which affects parallel data signal transmissions and for providing fault tolerance in large scale scalable systems, for instance used in trigger farms for high energy physics experiments. The SWIFT chip (SWItch for Fault Tolerance) is part of a cluster built around commercially components which has been inspired by the LHCb experiment. The skew is extremely important because it directly affects the sample window available to the receiver logic and either forces to use quality and expensive cables in order to minimize its effects or reduces the maximum signal transmission range or distance. This problem is handled by the deskewing circuitry at the SWIFT chip, which is able to match dynamically the signal transitions at the receiver link by adding an individual delay to each input signal in steps of 100 ps for LVDS signals up to 250 MHz. The deskew module is based on full custom analog delay units plus a digital skew detector block. A 16-bit processor is implemented for processing tasks. The chip compensates dynamically skews of LVDS signals up to 250 MHz in steps of 100 ps and adds fault tolerance to the farm of PCs by allowing the bypassing of a failing compute node to which is attached

Design of an integrated low-noise, low-power charge sensitive preamplifier for γ and particle spectroscopy with solid state detectors

The design of an integrated charge-sensitive preamplifier suitable for γ-ray spectroscopy is presented. It is fully integrated, except for the feedback resistor, and can drive directly a 50Ω cable with its low impedance output stage. It is designed in AMS 0.35μm technology and its small dimensions and low power consumption (10 mW) are optimized for multi-channel applications. It works both with germanium and silicon detectors for a large range of values of electrode and feedback capacitances. Its wide bandwidth ensures a risetime of 10 ns or less in most configurations. This characteristic makes the preamplifier suitable not only for high resolution spectroscopy but also for pulse-shape analysis. The most innovative part of the circuit is the input stage: generally in the field of γ spectroscopy a discrete low-noise JFET transistor is used, but this structure fails when physical dimensions and power consumptions are a concern. This fully-integrated input stage was designed in order to keep the noise parameters comparable with “state of the art” levels, and was conceived with flexibility in mind. It features a differential input structure, variable bandwidth and adjustable operation point.

Design and test of a high-speed flash ADC mezzanine card for high-resolution and timing performance in nuclear structure experiments

This work describes new electronics for the EXOGAM2 (HP-Ge detector array) and NEDA (BC501A-based neutron detector array). A new digitizing card with high resolution has been designed for gamma-ray and neutron spectroscopy experiments. The higher bandwidth requirement of the NEDA signals, together with the necessity for accuracy, require a high sampling rate in order to preserve the shape for real-time Pulse Shape Analysis (PSA). The PSA is of paramount importance for the NEDA to discriminate between neutrons and -ray signals. Both high resolution and high speed parameters are often difficult to achieve in a single electronic unit. These constraints, together with the need to build new digitizing electronics to improve performance and flexibility of signal analysis in nuclear physics experiments, led to the development a new FADC mezzanine card. In this work, the design and development are described, including the characterization procedure and the preliminary measurement results.

Development of the control card for the digitizers of the second generation electronics of AGATA

In this work, the features and development process of the novel control card for the digitizers of AGATA are presented. The board is part of the new hardware proposed for the electronic system of the experiment. In particular, the control card provides the sampling clock for the digitizers, contributes to the synchronization of the digital data and performs the slow control of its associated digitizer cards.