V. Rodellar

An associative memory to solve the mixture problem in composite spectra

Outlines the development of a robust method for the determination and quantification of the components in a composite radiation spectrum (CRS) assuming that the patterns of the individual nuclide spectra present in it are known in advance. A solution with a given miscalibration when the CRS is taken is also presented. The general solution method is based on the use of the pseudoinverse matrix supported by an associative memory, for which two different methods are presented. One is based on Pyles algorithm, and the other is based on an adaptive Widrow-Hoff procedure. The two methods are compared according to their computational complexity and the feasibility of their VLSI implementation.<<ETX>>

Computable minimum lattice-like ARMA synthesis

A cascade synthesis for autoregressive moving-average (ARMA) digital filters, which uses the minimum number of delay elements (the degree of the transfer function in z), is described. The resulting structure results in the very convenient lattice from when the zeros of the transmission are not on the unit circle. The theory rests on conversion to scattering parameters and the use of a Richards function, valid for complex zeros of rational functions with complex coefficients. Results of zeros of transmission on the unit circle are obtained by a parallel combination of lattices. By a suitable transformation, the sections are made computable while preserving the cascade form. >

A VLSI arithmetic unit for a signal processing neural network

The design of a VLSI arithmetic unit for the support of signal processing and neural network algorithms is discussed. The arithmetic unit is conceived to allow the execution of inner product operations maintaining the silicon area and development costs under reasonable limits, and allowing the parameterization of the design in a modular way. A serial-bit pipeline multiplier and a fixed-point number format have been successfully used. These aspects are justified by a study on the accuracy required when implementing certain signal processing and neural network algorithms, for which some numerical examples are given. A design of a whole chip incorporating such an arithmetic unit and the structure of the required control unit are outlined.<<ETX>>

A PARCOR characterization of the ear for hearing aids

A possible characterization of the ear through the PARCOR algorithm is suggested. This leads to a digital filter heating aid that could be of assistance in compensating for partial hearing loss.

Petri nets for robot lattices

An augmented lattice is introduced for the analysis of production lines of robots with the analysis set up using binary Petri-nets. It is known that the lattice production line configuration of robots is about the most flexible for industrial manufacturing. This lattice configuration is slightly extended to further increase the flexibility. This augmented lattice is investigated using a single-place, multiple transition model for the robot information flow and the connection decision making. Using this model and binary Petri-net theory, the equations describing the system are obtained for a cascade of n augmented lattices. From the equations, a discussion is given on prevention of net deadlock, system tolerance, and production efficiency.

Performance evaluation of reusable multipliers for rapid prototyping

A reusable multiplier operating in fixed-point and twos complement arithmetic is introduced. The data format and operand sizes can be adapted to the precision requirements for any particular DSP application. The algorithmic basis of the device resides in the utilization of signed digit arithmetic representation that allows an important degree of independence between the critical path delay and operands size. The model is written in VHDL. The performance results in terms of area requirement and critical path delay for Vixtex FPGA and 0.6 /spl mu/m AMS technologies are evaluated.

An inner ear hair cell parametrizable implementation

Through this paper the implementation of an inner ear model including macromechanics and hair-cell transduction is presented and discussed. Important characteristics of the design are the use of the well-known Meddis model for the transduction structure, and the methodology for Design with Reusability employed, which allows future design refinements on an FPGA for real-time speech processing and recognition.

Robust speech processing based on binaural hearing systems

Reliability is a key factor in the Spoken-Command Recognition. To increase recognition rates the methodology suggested in the present paper combines adaptive Joint-Process Estimation with Source Detection using Binaural-inspired Algorithms and Negative Beamforming. The paper proposes the use of these techniques in public transportation environments.

A digitally implementable ear-type lattice

The internal auditory system emits slightly detectable sounds (Kemp echoes) as a response to the auditory input. This response is able to be mimicked via a cascade of two-port lattices and has been previously simulated with analog amplifiers. This paper presents a digital implementation scheme using fixed-point, twos complement arithmetic with the wordlength and decimal precision based on generic parameters. The advantages are in accuracy and cancellation of initial cycle oscillations due to initial conditions normally present in both numerical and continuous implementations.

A VLSI architecture for the support of an auditory neural model for hearing and speech processing

A description is given of the VLSI implementation of a signal processor devoted to the support of both an auditory model and a neural model. The first one has been developed as a digital filter, and is able of separating a given speech trace in a set of channels producing a time-frequency representation of speech at a low rate, allowing large savings in computational complexity. The second model implements a phonetic coding scheme for Spanish using a time delay neural network. The signal processor has been designed using serial arithmetics, which allows large savings in area, and may be extended as a systolic system to implement the whole structure. The floorplan of the chip being designed is presented, and provisions for its proper operation as a single device or in an array are also given. The structure described may be used as a phonetic encoder in a connected speech recognition scheme or as a subsystem in hearing aids.<<ETX>>