Valerie Lines

66 MHz 2.3 M ternary dynamic content addressable memory

This paper describes a 66 MHz 2.3 M Content Addressable Memory (CAM) which uses DRAM technology for the basic ternary CAM cell. The chips architecture allows a high speed search operation and single cycle learning. The DRAM based cell structure enables implementation of a larger table size than is available in similar technology SRAM based CAMs. A new matchline sense amplifier allows fast, low power sensing of the matchline. Among the chips many features are a DDR input interface and the ability to cascade up to eight parts without additional logic. The density and speed of this part make it suitable for many applications such as network switching.

A 1GHz embedded DRAM macro and fully programmable BIST with at-speed bitmap capability

A 1GHz 2Mb embedded DRAM macro and an associated fully programmable BIST block have been designed in a 90nm logic based technology. The DRAM macro has 128-bit I/O, sixteen banks, 1 ns interleaved operation, 4ns random access read pipeline, and an early write scheme. The BIST is used for at-speed testing of the DRAM macro and can accumulate fail data for redundancy repair and bitmap generation. It can be cascaded and shared between memory macrocells.