Valeriu Beiu

VLSI implementations of threshold logic-a comprehensive survey

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

Majority multiplexing-economical redundant fault-tolerant designs for nanoarchitectures

Motivated by the need for economical fault-tolerant designs for nanoarchitectures, we explore a novel multiplexing-based redundant design scheme at small (/spl les/100) and very small (/spl les/10) redundancy factors. In particular, we adapt a strategy known as von Neumann multiplexing to circuits of majority gates with three inputs and for the first time exactly analyze the performance of a multiplexing scheme for very small redundancies, using combinatorial arguments. We also develop an extension of von Neumann multiplexing that further improves performance by excluding unnecessary restorative stages in the computation. Our results show that the optimized three-input majority multiplexing (MAJ-3 MUX) outperforms the latest scheme presented in the literature, known as parallel restitution (PAR-REST), by a factor between two and four, for 48/spl les/R/spl les/100. Our scheme performs extremely well at very small redundancies, for which our analysis is the only accurate one. Finally, we determine an upper bound on the maximum tolerable failure probability when any redundancy factor may be used. This bound clearly indicates the advantage of using three-input majority gates in terms of reliable operation.

On single electron technology full adders

This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.

On nanoelectronic architectural challenges and solutions

This paper discusses the many challenges in the design of future nano architectures that result from the use of nanoelectronic devices. The relations among these challenges are studied, and an unfortunately subjective relative ranking is proposed. Possible solutions are suggested.

On single-electron technology full adders

This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper provides a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This can allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, is described and compared with the other SET FAs.

Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates

Scaling complementary metal oxide semiconductor (CMOS) devices has been a method used very successfully over the last four decades to improve the performance and the functionality of very large scale integrated (VLSI) designs. Still, scaling is heading towards several fundamental limits as the feature size is being decreased towards 10 nm and less. One of the challenges associated with scaling is the expected increase of static and dynamic parameter fluctuations and variations, as well as intrinsic and extrinsic noises, with significant effects on reliability. Therefore, there is a clear, growing need for electronic design automation (EDA) tools that can predict the reliability of future massive nano-scaled designs with very high accuracy. Such tools are essential to help VLSI designers optimize the conflicting tradeoffs between area-power-delay and reliability requirements. In this paper, we introduce an EDA tool that quickly and accurately estimates the reliability of any CMOS gate. The tool improves the accuracy of the reliability calculation at the gate level by taking into consideration the gates topology, the reliability of the individual devices, the applied input vector, as well as the noise margins. It can also be used to estimate the effect on different types of faults and defects, and to estimate the effects of enhancing the reliability of individual devices on the gates overall reliability.

A novel highly reliable low-power nano architecture when von Neumann augments Kolmogorov

This work presents a novel architecture, which is both device and circuit independent. The starting idea is that computations can be performed in three fundamentally different ways: entirely digital (using Boolean gates), entirely analog (using analog circuits), or mixed (using both digital and analog circuits). The boundaries between these are sometimes very thin. As an example, a threshold logic gate is already mixed, i.e. even if the inputs and the output are Boolean, the weighted sum-of-inputs is a multiple-valued logic signal, i.e. a low-precision analog signal. It has already been suggested that, at least for CMOS, a mixed analog/digital approach is the most power-efficient solution. Still, the main disadvantages of using analog circuits are: (i) their more complex (handcrafted) design, and (ii) their (expected) lower reliability (signal-to-noise or precision), which will be exacerbated by scaling. Here, we will show how both these disadvantages could be tackled. A constructive solution for Kolmogorovs superposition and (multi-threshold) threshold logic synthesis could be used for automating the design. Digital or threshold logic circuits will compensate for the accumulation of noise in the cascaded (very) low precision analog circuits. These digital circuits will also contribute to a von Neumanns multiplexing scheme used to augment the defect- and fault-tolerance of the architecture. A few examples will show how this architectural approach could be mapped on top of a given (nano) technology.

On the circuit complexity of sigmoid feedforward neural networks

This paper aims to examine the circuit complexity of sigmoid activation feedforward artificial neural networks by placing them amongst several classic Boolean and threshold gate circuit complexity classes. The starting point is the class NN(k) defined by [Shawe-Taylor et al. (1992)] Classes of feedforward neural nets and their circuit complexity. Neural Networks 5(6), 971-977. For a better characterisation, we introduce two additional classes NN(k)(Delta) and NN(k)(Delta,epsilon) having less restrictive conditions than NN(k) concerning fan-in and accuracy, and proceed to prove relations amongst these three classes and well established circuit complexity classes. For doing that, a particular class of Boolean functions F(Delta) is first introduced and we show how a threshold gate circuit can be recursively built for any f(Delta) belonging to F(Delta). As the G-functions (computing the carries) are f(Delta) functions, a class of solutions is obtained for threshold gate adders. We then constructively prove the inclusions amongst circuit complexity classes. This is done by converting the sigmoid feedforward artificial neural network into an equivalent threshold gate circuit [Shawe-Taylor et al. (1992)]. Each threshold gate is then replaced by a multiple input adder having a binary tree structure, relaxing the logarithmic fan-in condition from ([Shawe-Taylor et al. 1992]) to (almost) polynomial. This means that larger classes of sigmoid activation feedforward neural networks can be implemented in polynomial size Boolean circuits with a small constant fan-in at the expense of a logarithmic factor increase in the number of layers. Similar results are obtained for threshold circuits, and are liked with the previous ones. The main conclusion is that there are interesting fan-in dependent depth-size tradeoffs when trying to digitally implement sigmoid activation feedforward neural networks. Copyright 1996 Elsevier Science Ltd

Design and analysis of SET circuits: using MATLAB modules and SIMON

This paper describes two MATLAB modules which have been developed for enhancing SIMON, a Monte Carlo simulator for single electron technology (SET) circuits. The first module facilitates the hierarchical design of larger SET circuits, and has: (i) a sub-module that builds a larger circuit - starting from a library of gates; while (ii) another sub-module allows for an easier specification of the input signals. The second module allows for the statistical analysis of SET circuits. The usefulness of the two modules has already been established through: (i) the design, simulation, and characterization of an advanced 16-bit capacitive SET threshold logic adder; (ii) the comparison of many different SET full adders; (iii) an analysis of the sensitivity to variations of different SET gates; and (iv) an analysis of a novel fault-tolerant architecture based on multiplexing.

Low-power and highly reliable logic gates transistor-level optimizations

Power dissipation and reliability are two major challenges when designing gates and circuits using nanoscale devices. This paper proposes a novel approach for the design of CMOS logic gates which aims to simultaneously decrease their power consumption and their probabilities of failure. This new sizing method was evaluated on CMOS inverters and NOR-2 gates at three technology nodes: 16nm, 22nm, and 32nm. The new inverters and NOR-2 were compared to the classic gates. The results show that the new gates have significantly lower power and higher reliability when compared to classic CMOS gates. The results also suggest that the advantages of the new design method are enhanced at smaller feature sizes: at 16nm the new gates outperform the classic ones in reliability, power, and PDP.