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Dive into the research topics where Vasileios Tsoutsouras is active.

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Featured researches published by Vasileios Tsoutsouras.


international conference on hardware/software codesign and system synthesis | 2016

Distributed QoS management for internet of things under resource constraints

Farzad Samie; Vasileios Tsoutsouras; Sotirios Xydis; Lars Bauer; Dimitrios Soudris; Jörg Henkel

Internet-of-Things (IoT) envisions an infrastructure of ubiquitous networked smart devices offering advanced monitoring and control services. Current art in IoT architectures utilizes gateways to enable application-specific connectivity to IoT devices. In typical configurations, an IoT gateway is shared among several IoT devices. However, given the limited available bandwidth and processing capabilities of an IoT gateway, the quality of service (QoS) of IoT devices must be adjusted over time not only to fulfill the needs of individual IoT device users, but also to tolerate the QoS needs of the other IoT devices sharing the same gateway. In this paper, we address the problem of QoS management for IoT devices under bandwidth, battery, and processing constraints. We first formulate the problem of resource-aware QoS tailored to the IoT paradigm and then propose an efficient problem decomposition that enables the adoption of a recurrent dynamic programming approach with reduced execution time overhead. We evaluate the efficiency of the proposed approach with a case study and through extensive experimentation over different IoT system configurations regarding to the number and type of the employed IoT-devices. Experiments show that our solution improves the overall QoS by 50% compared to an unsupervised system while both meet the constraints.


the internet of things | 2016

Computation offloading and resource allocation for low-power IoT edge devices

Farzad Samie; Vasileios Tsoutsouras; Lars Bauer; Sotirios Xydis; Dimitrios Soudris; Jörg Henkel

With the proliferation of portable and mobile IoT devices and their increasing processing capability, we witness that the edge of network is moving to the IoT gateways and smart devices. To avoid Big Data issues (e.g. high latency of cloud based IoT), the processing of the captured data is starting from the IoT edge node. However, the available processing capabilities and energy resources are still limited and do not allow to fully process the data on-board. It calls for offloading some portions of computation to the gateway or servers. Due to the limited bandwidth of the IoT gateways, choosing the offloading levels of connected devices and allocating bandwidth to them is a challenging problem. This paper proposes a technique for managing computation offloading in a local IoT network under bandwidth constraints. The existing bandwidth allocation and computation offloading management techniques underutilize the gateways resources (e.g. bandwidth) due to the fragmentation issue. This issue stems from the discrete coarse-grained choices (i.e. offloading levels) on the IoT end nodes. Our proposed technique addresses this issue, and utilizes the available resources of the gateway effectively. The experimental results show on average 1 hour (up to 1.5 hour) improvement in battery life of edge devices. The utilization of gateways bandwidth increased by 40%.


signal processing systems | 2017

An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC

Vasileios Tsoutsouras; Konstantina Koliogeorgi; Sotirios Xydis; Dimitrios Soudris

In recent years, Support Vector Machine (SVM) classifiers have played a crucial role in providing data fusion and high accuracy classification solutions for various, complex, non-linear problems. Their popularity accompanied by the ever-increasing need of implementing it on computationally weak, portable or even wearable systems has refueled the effort to accelerate their execution. In this paper, we explore FPGA-based acceleration to produce efficient SVM hardware co-processors. We propose a systematic two-level approach for SVM acceleration, which first optimizes the global structure of the original SVM’s behavioral description to exploit the data- and instruction-level parallelism and then further refines it through a targeted design exploration that matches the accelerator’s memory architecture to its computation and memory access patterns. The proposed methodology has been implemented as a framework on top of Vivado High-Level Synthesis (HLS) tool. We evaluate the effectiveness of the methodology through a rich set of analysis and validation results, which show that its adoption delivers SVM accelerator designs achieving latency gains of up to 98.78 % in respect to Vivado-HLS default optimized solution. Finally, using as a case study an ECG analysis and Arrhythmia detection system we show that a target Zynq programmable SoC utilizing the optimized SVM accelerator design outperforms pure software implementations in numerous single or dual core target platforms, achieving speedups, which range from 10 × up to 78 ×.


power and timing modeling optimization and simulation | 2016

Energy profile analysis of Zynq-7000 programmable SoC for embedded medical processing: Study on ECG arrhythmia detection

Konstantinos Railis; Vasileios Tsoutsouras; Sotirios Xydis; Dimitrios Soudris

Electrocardiogram (ECG) analysis has been established as a key element regarding the evaluation of the human health status. The computational complexity along with the strict constraints of real-time assessment of a heart beat, has made the ECG analysis flow a very challenging application for embedded medical devices. Recent advancements in cyber-physical and IoT systems are transforming medical processing towards embedded and wearable devices, thus making energy consumption a first class design objective. In this work, we focus on analysing the power, performance and energy profiles of an ECG analysis and arrhythmia detection software pipeline during its execution on a ZYNQ-based SoC. We evaluate a large set of design alternatives spanning from a pure software-only implementation to HW/SW oriented designs, in which High-Level Synthesis capabilities are utilized. Using the medically validated MIT-BIH ECG database, we examine the efficiency and the sensitivity of the design solutions in different operating frequencies and examine three Quality of Service (QoS) levels concerning the sampling rate of the ECG signal.


applied reconfigurable computing | 2015

SWAN-iCARE Project: On the Efficiency of FPGAs Emulating Wearable Medical Devices for Wound Management and Monitoring

Vasileios Tsoutsouras; Sotirios Xydis; Dimitrios Soudris; L. Lymperopoulos

In this paper we examine the efficiency of FPGA-based reconfigurable systems for emulating complex embedded medical devices. We focus our analysis on embedded wearable medical devices targeting remote wound monitoring and management. The application scenario originates from the Swan-iCare EU funded project which aims at developing an integrated autonomous device for the monitoring and personalized management of chronic wounds, mainly diabetic foot ulcers and venous leg ulcers. Taking into account the functional requirements of such medical systems, we show that FPGA based functional emulation forms a promising solution that enables easy programming of bare-metal medical applications with micro-architectural and port connectivity/availability characteristics matching well the requirements of the specific application domain. The hardware platform and the embedded software for the supported medical application are described in detail and a set of qualitative and quantitative evaluations are provided to show the effectiveness of the approach.


the internet of things | 2018

Distributed Trade-Based Edge Device Management in Multi-Gateway IoT

Farzad Samie; Vasileios Tsoutsouras; Lars Bauer; Sotirios Xydis; Dimitrios Soudris; Jörg Henkel

The Internet-of-Things (IoT) envisions an infrastructure of ubiquitous networked smart devices offering advanced monitoring and control services. The current art in IoT architectures utilizes gateways to enable application-specific connectivity to IoT devices. In typical configurations, IoT gateways are shared among several IoT edge devices. Given the limited available bandwidth and processing capabilities of an IoT gateway, the service quality (SQ) of connected IoT edge devices must be adjusted over time not only to fulfill the needs of individual IoT device users but also to tolerate the SQ needs of the other IoT edge devices sharing the same gateway. However, having multiple gateways introduces an interdependent problem, the binding, i.e., which IoT device shall connect to which gateway. In this article, we jointly address the binding and allocation problems of IoT edge devices in a multigateway system under the constraints of available bandwidth, processing power, and battery lifetime. We propose a distributed trade-based mechanism in which after an initial setup, gateways negotiate and trade the IoT edge devices to increase the overall SQ. We evaluate the efficiency of the proposed approach with a case study and through extensive experimentation over different IoT system configurations regarding the number and type of the employed IoT edge devices. Experiments show that our solution improves the overall SQ by up to 56% compared to an unsupervised system. Our solution also achieves up to 24.6% improvement on overall SQ compared to the state-of-the-art SQ management scheme, while they both meet the battery lifetime constraints of the IoT devices.


ACM Transactions in Embedded Computing Systems | 2018

A Hierarchical Distributed Runtime Resource Management Scheme for NoC-Based Many-Cores

Vasileios Tsoutsouras; Iraklis Anagnostopoulos; Dimosthenis Masouros; Dimitrios Soudris

As technology constantly strengthens its presence in all aspects of human life, computing systems integrate a high number of processing cores, whereas applications become more complex and greedy for computational resources. Inevitably, this high increase in processing elements combined with the unpredictable resource requirements of executed applications at design time impose new design constraints to resource management of many-core systems, turning the distributed functionality into a necessity. In this work, we present a distributed runtime resource management framework for many-core systems utilizing a network-on-chip (NoC) infrastructure. Specifically, we couple the concept of distributed management with parallel applications by assigning different roles to the available computing resources. The presented design is based on the idea of local controllers and managers, whereas an on-chip intercommunication scheme ensures decision distribution. The evaluation of the proposed framework was performed on an Intel Single-Chip Cloud Computer, an actual NoC-based, many-core system. Experimental results show that the proposed scheme manages to allocate resources efficiently at runtime, leading to gains of up to 30% in application execution latency compared to relevant state-of-the-art distributed resource management frameworks.


Archive | 2017

Software Design and Optimization of ECG Signal Analysis and Diagnosis for Embedded IoT Devices

Vasileios Tsoutsouras; Dimitra Azariadi; Konstantina Koliogewrgi; Sotirios Xydis; Dimitrios Soudris

The medical domain is one of the most rapidly expanding application areas of Internet of Things (IoT) technology. For chronic diseases, this technology can be highly useful for the patient, providing constant monitoring and ability for timely intervention of medical staff in case of an emergency. This intended system behavior imposes new requirements to the design and implementation of processing flows implemented on embedded IoT devices which are already constrained by limited computational capabilities and power budget. This work aims at designing and implementing such a bio-medical signal analysis flow based on the case study of arrhythmia detection using electrocardiogram signals and machine learning techniques. Different architectural decisions of the flow are explored at high level and the final optimized version is implemented on a state-of-the-art IoT node. The evaluation of the execution flow on this device provides information on the actual requirements of each sub-component of the flow combined with an analysis of its behavior as computational requirements of the machine learning algorithms scale up.


ACM Transactions in Embedded Computing Systems | 2017

SoftRM: Self-Organized Fault-Tolerant Resource Management for Failure Detection and Recovery in NoC Based Many-Cores

Vasileios Tsoutsouras; Dimosthenis Masouros; Sotirios Xydis; Dimitrios Soudris

Many-core systems are envisioned to leverage the ever-increasing demand for more powerful computing systems. To provide the necessary computing power, the number of Processing Elements integrated on-chip increases and NoC based infrastructures are adopted to address the interconnection scalability. The advent of these new architectures surfaces the need for more sophisticated, distributed resource management paradigms, which in addition to the extreme integration scaling, make the new systems more prone to errors manifested both at hardware and software. In this work, we highlight the need for Run-Time Resource management to be enhanced with fault tolerance features and propose SoftRM, a resource management framework which can dynamically adapt to permanent failures in a self-organized, workload-aware manner. Self-organization allows the resource management agents to recover from a failure in a coordinated way by electing a new agent to replace the failed one, while workload awareness optimizes this choice according to the status of each core. We evaluate the proposed framework on Intel Single-chip Cloud Computer (SCC), a NoC based many-core system and customize it to achieve minimum interference on the resource allocation process. We showcase that its workload-aware features manage to utilize free resources in more that 90% of the conducted experiments. Comparison with relevant state-of-the-art fault tolerant frameworks shows decrease of up to 67% in the imposed overhead on application execution.


power and timing modeling optimization and simulation | 2017

From edge to cloud: Design and implementation of a healthcare Internet of Things infrastructure

Dimosthenis Masouros; Ioannis Bakolas; Vasileios Tsoutsouras; Kostas Siozios; Dimitrios Soudris

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Dimitrios Soudris

National Technical University of Athens

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Sotirios Xydis

National Technical University of Athens

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Dimosthenis Masouros

National Technical University of Athens

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Farzad Samie

Karlsruhe Institute of Technology

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Jörg Henkel

Karlsruhe Institute of Technology

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Lars Bauer

Karlsruhe Institute of Technology

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Charalampos Marantos

National Technical University of Athens

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Dimitra Azariadi

National Technical University of Athens

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Ioannis Bakolas

National Technical University of Athens

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Kiamal Z. Pekmestzi

National Technical University of Athens

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