Vasilis F. Pavlidis

3-D Topologies for Networks-on-Chip

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.

Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for two-dimensional circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits while considering different forms of vertical integration, such as system-in-package and 3-D ICs with fine grain vertical interconnections. Global signaling issues, such as clock and power distribution networks, are further exacerbated in vertical integration due to the limited number of package pins, the distance of these pins from other planes within the 3-D system, and the impedance characteristics of the through silicon vias (TSVs). In addition to these dedicated networks, global signaling techniques that incorporate the diverse traits of complex 3-D systems are required. One possible approach, potentially significantly reducing the complexity of interconnect issues in 3-D circuits, is 3-D networks-on-chip (NoC). Design methodologies that exploit the diversity of 3-D structures to further enhance the performance of multiplane integrated systems are necessary. The longest interconnects within a 3-D circuit are those interconnects comprising several TSVs and traversing multiple physical planes. Consequently, minimizing the delay of the interplane nets is of great importance. By considering the nonuniform impedance characteristics of the interplane interconnects while placing the TSVs, the delay of these nets is decreased. In addition, the difference in electrical behavior between the horizontal and vertical interconnects suggests that asymmetric structures can be useful candidates for distributing the clock signal within a 3-D circuit. A 3-D test circuit fabricated with a 180 nm silicon-on-insulator (SOI) technology, manufactured by MIT Lincoln Laboratories, exploring several clock distribution topologies is described. Correct operation at 1 GHz has been demonstrated. Several 3-D NoC topologies incorporating dissimilar 3-D interconnect structures are reviewed as a promising solution for communication limited systems-on-chip (SoC). Appropriate performance models are described to evaluate these topologies. Several forms of vertical integration, such as system-in-package and different candidate technologies for 3-D circuits, such as SOI, are considered. The techniques described in this paper address fundamental interconnect structures in the 3-D design process. Several interesting research problems in the design of 3-D circuits are also discussed.

Clock distribution networks for 3-D ictegrated Circuits

Three-dimensional (3D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3D clock distribution network topologies is presented in this paper. Experimental results of a 3D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.

Performance analysis of 3-D monolithic integrated circuits

3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (FSVs). Given the advantage of such small contacts, 3DMI supports stacking active layers such that fine-grain integration of 3-D circuits can be implemented. This paper extends the idea of constructing the standard cells across two active layers, forming 3-D cells, to reduce the overall area and interconnect wirelength of a circuit. To demonstrate the effect of the 3DMI technology on these important parameters of circuit design, two important communication blocks are evaluated. Specifically, a low-density-parity-check (LDPC) decoder as a sample of interconnect-dominated circuit and a data-encryption-standard (DES) block, which is good instance of a gate dominated circuit, are investigated. By employing 3-D cells in the conventional design flow chain, there is more than 10% decrease in wirelength for both circuits (in wirelength driven placement mode). However, when subjected to timing driven placement a slight reduction in delay (1.6%) is observed for an LDPC decoder, whereas for the DES block considerable delay reduction (14.22%) is achieved.

Interconnect delay minimization through interlayer via placement in 3-D ICs

The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line connecting two circuits on different planes is determined. The optimum vertical through via location and length or, equivalently, the number of physical planes traversed by the vertical through via, are determined for varying the placement of the connected circuits. Design expressions for the optimal via locations and lengths have been developed to support placement and routing algorithms for 3-D ICs.

Clock Distribution Networks in 3-D Integrated Systems

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.

Analytical heat transfer model for thermal through-silicon vias

Thermal issues are one of the primary challenges in 3-D integrated circuits. Thermal through-silicon vias (TTSVs) are considered an effective means to reduce the temperature of 3-D ICs. The effect of the physical and technological parameters of TTSVs on the heat transfer process within 3-D ICs is investigated. Two resistive networks are utilized to model the physical behavior of TTSVs. Based on these models, closed-form expressions are provided describing the flow of heat through TTSVs within a 3-D IC. The accuracy of these models is compared with results from a commercial FEM tool. For an investigated three-plane circuit, the average error of the first and second models is 2% and 4%, respectively. The effect of the physical parameters of TTSVs on the resulting temperature is described through the proposed models. For example, the temperature changes non-monotonically with the thickness of the silicon substrate. This behavior is not described by the traditional single thermal resistance model. The proposed models are used for the thermal analysis of a 3-D DRAM-μP system where the conventional model is shown to considerably overestimate the temperature of the system.

Power distribution paths in 3-D ICS

Distributing power and ground to a vertically integrated system is a complex and difficult task. Interplane communication and power delivery are achieved by through silicon vias (TSVs) in most of the manufacturing techniques for three-dimensional (3-D) circuits. As shown in this paper, these vertical interconnects provide additional low impedance paths for distributing power and ground within a 3-D circuit. These paths, however, have not been considered in the design process of 3-D power and ground distribution networks. By exploiting these additional paths, the IR drop within each plane is reduced. Alternatively, the routing congestion caused by the TSVs can be decreased by removing stacks of metal vias that are used within a power distribution network. Additionally, the required decoupling capacitance for a circuit can be reduced, resulting in significant savings in area. Case studies of power grids demonstrate a significant reduction of 22% in the number of intraplane vias. Alternatively, a 25% decrease in the decoupling capacitance can be achieved.

A novel framework for exploring 3-D FPGAs with heterogeneous interconnect fabric

A heterogeneous interconnect architecture can be a useful approach for the design of 3-D FPGAs. A methodology to investigate heterogeneous interconnection schemes for 3-D FPGAs under different 3-D fabrication technologies is proposed. Application of the proposed methodology on benchmark circuits demonstrates an improvement in delay, power consumption, and total wire-length of approximately 41%, 32%, and 36%, respectively, as compared to 2-D FPGAs. These improvements are additional to reducing the number of interlayer connections. The fewer interlayer connections are traded off for a higher yield. An area model to evaluate this trade-off is presented. Results indicate that a heterogeneous 3-D FPGA requires 37% less area as compared to a homogeneous 3-D FPGA. Consequently, the heterogeneous FPGAs can exhibit a higher manufacturing yield. A design toolset is also developed to support the design and exploration of various performance metrics for the proposed 3-D FPGAs.

The combined effect of process variations and power supply noise on clock skew and jitter

In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations. The combined effect of process variations and power supply noise on clock skew and jitter is investigated in this paper. A statistical model of skitter, which consists of skew and jitter, is proposed. Clock paths with different buffer insertion strategies are compared in terms of skew and jitter. The tradeoffs among the constraints on clock jitter, skew, slew rate, and power are discussed. For strict timing constraints, severe power overhead (≥110%) has to be added to obtain a low improvement in the worst case skitter and slew rate (≤13%). The effect of widely-used techniques, such as recombinant trees and dynamic voltage scaling, on decreasing skitter is also investigated.