Vassilios Gerousis

Impact of a SADP flow on the design and process for N10/N7 Metal layers

This work addresses the difficulties in creating a manufacturable M2 layer based on an SADP process for N10/N7 and proposes a couple of solutions. For the N10 design, we opted for a line staggering approach in which each line-end ends on a contact. We highlight the challenges to obtain a reasonable process window, both in simulation as on based on exposures on wafer. The main challenges come from a very complex keep mask, consisting of complicated 2D structures which are very challenging for 193i litho. Therefore, we propose a solution in which we perform a traditional LELE process on top of a mandrel layer. Towards N7 we show that a line staggering approach starts to break down and design needs to allow better process window for lithography by having metal lines ending in an aligned fashion. has many challenges and we propose to switch to a line cut approach. A more lithography friendly approach is needed for design where the lines end at aligned points so that the process window can be enhanced.

Demonstrating production quality multiple exposure patterning aware routing for the 10NM node

This paper reviews the escalation in design constraints imposed on 2nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. ~45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.

IC-package co-design and analysis for 3D-IC designs

The implementation of a 3D IC is typically accomplished by multiple design teams, in multiple geographies, using a variety of design tools. Types of designs include a simple package, with an analog die and a digital die placed side-by-side and more complex designs include die stacks of multiple analog or digital dies in face-to-face configurations connecting with micro bumps. Through-silicon-vias (TSVs) provide an extra level of complexity allowing an individual die to connect to the component below and above it in the stack. Interposers (silicon or organic) provide greater functional density, performance, and reduced cost. Also used in 3D-IC design are package-in-package, and package-on-package design styles. This paper discusses five key ingredients necessary for the successful design of a 3D-IC regardless which method above is used. These five items are • Logical system-level integration to connect the system of ICs and packages, including support of layout-vs-schematic (LVS) checks • Physical co-design across IC and package boundaries through the sharing of component abstracts and cross-fabric functionality • Timing, power, and thermal-based design of the 3D-IC system in context of the package • Package-aware system simulation of 3D-IC circuitry • Management of physical and logical engineering change orders (ECOs)

Low track height standard cell design in iN7 using scaling boosters

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

Metal stack optimization for low-power and high-density for N7-N5

One of the key challenges while scaling logic down to N7 and N5 is the requirement of self-aligned multiple patterning for the metal stack. This comes with a large cost of the backend cost and therefore a careful stack optimization is required. Various layers in the stack have different purposes and therefore their choice of pitch and number of layers is critical. Furthermore, when in ultra scaled dimensions of N7 or N5, the number of patterning options are also much larger ranging from multiple LE, EUV to SADP/SAQP. The right choice of these are also needed patterning techniques that use a full grating of wires like SADP/SAQP techniques introduce high level of metal dummies into the design. This implies a large capacitance penalty to the design therefore having large performance and power penalties. This is often mitigated with extra masking strategies. This paper discusses a holistic view of metal stack optimization from standard cell level all the way to routing and the corresponding trade-off that exist for this space.

Case study and efficient modelling for variational chemical-mechanical planarisation

Chemical-mechanical planarisation (CMP) is an enabling technique to achieve wafer planarity in backend manufacturing processes of integrated circuits. However, CMP also causes variations in metal and dielectric thicknesses because of the non-uniformity of metal feature density. The authors first conducted a case study of CMP-induced variations using an industrial CMP simulator together with a widely used microprocessor hardcore fabricated in a 90 nm technology with eight metal layers and a system-on-chip design fabricated in a 65 nm technology with four metal layers. They revealed a few interesting characteristics on thickness variations and, particularly, vertical and horizontal correlations between variations, although such correlations have been virtually ignored by the existing study on layout optimisation. These characteristics may lead to better modelling and design optimisation for CMP variations. As an example, the authors then proposed a stochastic CMP model to efficiently incorporate CMP variations estimation in the design flow and developed two algorithms to reduce the CMP simulation runs by 7x and 3x , respectively, when compared with generating the stochastic CMP model by detailed CMP simulations.

Pre-PDK block-level PPAC assessment of technology options for sub-7nm high-performance logic

This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two architectures examined in this paper differ primarily in their use of different power-distribution-networks to achieve the desired circuit performance for high-performance logic designs. The paper shows the importance of incorporating block-level routability experiments in the early phases of design-technology co-optimization by reviewing a series of routing trials that explore different aspects of the technology definition. Since the electrical and physical parameters leading to critical process assumptions and design rules are unique to specific integration schemes and design objectives, it is understood that the goal of this work is not to promote one cell-architecture over another, but rather to convey the importance of exploring critical trade-offs long before the process details of the technology node are finalized to a point where a process design kit can be published.

Track height reduction for standard-cell in below 5nm node: how low can you go?

The targeted 5nm and below technology node at IMEC has been defined by poly pitch 42nm and metal pitch 21nm. Compared to the previous node the CPP [1] remains the same and only the metal pitch is scaled down, which implies that direct pitch scaling will not lead to the most optimum scaling. Therefore, Standard Cell (SDC) track height reduction is a knob that can be used to achieve advances in the scaling of the technology to preserve Moore’s law. Here we present some of the options for the standard cell design that may enable this advance technology node and will require scaling boosters as Design-Technology co-optimization (DTCO).

Efficient place and route enablement of 5-tracks standard- cells through EUV compatible N5 ruleset

In imec predictive N5 technology platform (poly pitch 42nm, metal pitch 32nm), enabling cell height reduction from 6 to 5 tracks constitutes an interesting opportunity to reduce area of digital IP-blocks without increasing wafer cost. From a physical point of view, the two main challenges of reducing the number of tracks are posed by the increased difficulty of completing inter-cell connections in standard cell design, and by increased pin density that makes more challenging for the router to maintain high placement densities. Both these issues can potentially result into cell and chip area enlargement, thus mitigating or canceling the benefits of moving to 5-Tracks. In this study this side effect was avoided through a careful Design-Technology Co-Optimization approach (DTCO) [1], where a set of design arcs was used in conjunction with an EUV compatible ruleset that allowed efficient 5-Tracks standard cell design, resulting in final area gains up to 17% that were validated through a commercial state-of-the-art Place and Route (P&R) flow.

Low track height standard-cells enable high-placement density and low-BEOL cost (Conference Presentation)

Making standards cells smaller by lowering the cell height from 7.5 tracks to 6 tracks for the same set of ground rules is an efficient way to reduce area for high density digital IP blocks without increasing wafer cost. Denser cells however also imply a higher pin density and possible more routing congestion because of that. In Place and Route phase, this limits the cell density (a.k.a. utilization) that can be reached without design rule violations. This study shows that 6-track cells (192nm high) and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Standard cells have been created for 7.5T and 6T cells in N5 technology (poly pitch 42nm, metal pitch 32nm). The cells use a first horizontal routing layer (Mint) and vertical M1 for 1D intra-cell routing as much as possible. Place and route was performed on an opencores LDPC decoder. Various cell architectures and place and route optimizations are used to scale down the cell area and improve density. Most are not process optimizations, but optimized cell architectures and routing methods: • Open M1: M1 is removed as much as possible. This allows the router to use M1 for inter-cell routing in dense areas. • Routing in Mint: With open M1 the router can also use Mint to extend pins to access nearby free M1 tracks in congested areas. • Outbound rail: The 7.5T cells have inbound VDD/VSS rails in Mint for easy supply tapping. Moving the Mint rail outbound and shared between cells is required to enable lower track height cells. • Vertical Power distribution network (PDN): in 6T cells too many horizontal tracks would be consumed by the wide M2 rail. Mint is used instead combined with a vertical PDN in M1. • Self-Aligned Gate Contact allows to contact the gate on top of active fins. Any Mint track then can contact a gate, reducing cell area considerably. • Partially landing Mint Via trench: In 6T cells, a continuous Via trench underneath the Mint rail is used. This via partially lands on M0A to relax tip-to-tip requirements. • Relaxed M2 pitch: When pin access is handled in Mint and M1, this allows for a relaxed M2 pitch (48nm) with cheaper double patterning. To avoid horizontal routing layer congestion with the smaller cells, the 6T cells depend on the vertical PDN and open M1 to improve routability and pin access. Already in 7.5T cells, open M1 and vertical PDN help to improve routable utilization from 50% with closed M1 to 85% maximum. Moving to 6T cells, the combination of reduced cell area and high 85% utilization of result in a 60% area reduction vs the original 7.5T cells. We have shown that combining 6-track cells and smart routing results in up to 60% lower area than 7.5-track cells in N5 technology. Open M1 and vertical PDN are main area boosters for any cell architecture, boosting utilization from 50% to 85% already for the 7.5T cells.