Is this you? Create Your Porfile
Avatar

Venkat Iyer

Fairchild Semiconductor International, Inc.

Network

Latest external collaboration on country level. Dive into details by clicking on the dots.

Explore More

Hotspot

Dive into the research topics where Venkat Iyer is active.

Explore More

Publication

Featured researches published by Venkat Iyer.

Archive | 2006

Semiconductor die package and method for making the same

Oseob Jeon; Yoonhwa Choi; Boon Huan Gooi; Maria Cristina B. Estacio; David Chong; Tan Teik Keng; Shi-baek Nam; Rajeev Joshi; Chung-Lin Wu; Venkat Iyer; Lay Yeap Lim; Byoungok Lee

Archive | 2007

Semiconductor die package using leadframe and clip and method of manufacturing

Erwin Victor R. Cruz; Elsie Cabahug; Ti Ching Shian; Venkat Iyer

Archive | 2006

Semiconductor die package including multiple dies and a common node structure

Rajeev Joshi; Venkat Iyer; Jonathan Klein

Archive | 2005

Method to manufacture a universal footprint for a package with exposed chip

Jonathan A. Noquil; Connie Tangpuz; Romel N. Manatad; Stephen Martin; Rajeev Joshi; Venkat Iyer

Archive | 2008

Halbleiterchipgehäuse mit einem Leitungsrahmen und einem Clip sowie Verfahren zur Herstellung

Erwin Victor R. Cruz; Elsie Cabahug; Ti Ching Shian; Venkat Iyer

Archive | 2006

Boitier de puce semi-conductrice et son procede de fabrication

Oseob Jeon; Yoonhwa Choi; Boon Huan Gooi; Maria Cristina B. Estacio; David Chong; Tan Teik Keng; Shi-baek Nam; Rajeev Joshi; Chung-Lin Wu; Venkat Iyer; Lay Yeap Lim; Buyong-Ok Puchon Lee

Archive | 2005

Halbleiterchipgehäuse beinhaltend Universal-Anschlussfläche und Verfahren zur Herstellung derselben

Venkat Iyer; Rajeev Cupertino Joshi; Romel N. Manatad; Stephen Martin; Jonathan A. Noquil; Connie Tangpuz

Archive | 2005

Boitier pour des de semiconducteurs presentant un encombrement universel, et procede de fabrication du boitier

Rajeev Joshi; Venkat Iyer; Stephen Martin; Jonathan A. Noquil; Connie Tangpuz; Romel N. Manatad

Archive | 2005

Halbleiterchipgehäuse beinhaltend Universal-Anschlussfläche und Verfahren zur Herstellung derselben A semiconductor chip package comprising Universal pad and method for making the same

Venkat Iyer; Rajeev Cupertino Joshi; Romel N. Manatad; Stephen Martin; Jonathan A. Noquil; Connie Tangpuz

Archive | 2005

Procede de fabrication d'un empreinte de plots universelle pour un boitier avec une puce exposee

Jonathan A. Noquil; Connie Tangpuz; Romel N. Manatad; Stephen Martin; Rajeev Joshi; Venkat Iyer

Explore More

Collaboration

Dive into the Venkat Iyer's collaboration.

Explore More
Researchain Logo
Decentralizing Knowledge