Venkat Rangan

A subthreshold aVLSI implementation of the Izhikevich simple neuron model

We present a circuit architecture for compact analog VLSI implementation of the Izhikevich neuron model, which efficiently describes a wide variety of neuron spiking and bursting dynamics using two state variables and four adjustable parameters. Log-domain circuit design utilizing MOS transistors in subthreshold results in high energy efficiency, with less than 1pJ of energy consumed per spike. We also discuss the effects of parameter variations on the dynamics of the equations, and present simulation results that replicate several types of neural dynamics. The low power operation and compact analog VLSI realization make the architecture suitable for human-machine interface applications in neural prostheses and implantable bioelectronics, as well as large-scale neural emulation tools for computational neuroscience.

Subthreshold MOS dynamic translinear neural and synaptic conductance

Recent advances in neuromorphic engineering for brain-like computing and neural prostheses are converging towards realization of electronic synaptic arrays approaching the integration density and energy efficiency of the human brain. A major impediment in this development is practical realization of complex conductance-based models of biophysical neural and synaptic dynamics in nanoscale electronics. Here we present such highly compact and low-power realizations, where each conductance is implemented using a single MOS transistor operating in subthreshold. Three alternative realizations are shown, implementing log-domain transformations of the conductance-based dynamics using translinear current scaling, capacitance scaling, and voltage scaling. Transistor level simulations validate the linearity of single transistor neural and synaptic conductance-capacitance dynamics in a 90nm CMOS process.