Veronique Soulière

Process Optimisation for 4H-SiC MOSFET Applications

We report on 4H-SiC MOSFET devices implemented on p-type <11-20>-oriented epitaxial layers, using a two-step procedure for gate oxide formation. First is a thin, dry, thermal SiO2 layer grown at 1050°C for 1 hour. Next, is a thick (50 nm) layer of complementary oxide deposited by PECVD using TEOS as gas precursor. With respect to the standard thermal oxidation process, this results in much improvement of the field effect mobility. For the best samples, we find a peak value in the range of 330 cm2/Vs while, on the full wafer, an average mobility of about 160 cm2/Vs is found. Up to now, this is one of the best results ever reported for 4H-SiC MOSFETs.

Comparative Studies of 4H-SiC Layers Grown with Either Silane or HexaMethylDisilane / Propane Precursor Systems

We compare two series of 4H-SiC layers grown with either silane/propane or hexamethyldisilane/propane precursor systems. In both cases, the growth rate increases with precursor flow. However it saturates and, then, tend to decrease at high temperature. The range of growth conditions (C/Si ratio, growth rate, growth temperature) which give good surface morphology has been studied. The operating windows are identical for the two systems .In both cases, micro-Raman and LTPL spectroscopy confirm the formation of high quality 4H-SiC polytype.

Electrical Characteristics of Schottky Contacts on Ge-Doped 4H-SiC

We report on the electrical characteristics of Ni/4H-SiC Schottky contacts fabricated on a Ge-doped 4H-SiC epilayer. The morphology and the current mapping carried out by conductive atomic force microscopy on the epilayer allowed observing nanoscale preferential conductive paths on the sample surface. The electrical characteristics of Ni contacts have been studied before and after a rapid thermal annealing process. A highly inhomogeneous Schottky barrier was observed in as-deposited diodes, probably related to the surface electrical inhomogeneities of the 4H-SiC epilayer. A significant improvement of the Schottky diodes characteristics was achieved after annealing at 700°C, leading to the consumption of the near surface epilayer region by Ni/4H-SiC reaction. After this treatment, the temperature behavior of the ideality factor and Schottky barrier height was comparable to that observed on commercial 4H-SiC material.

Buried Selective Growth of p-Doped SiC by VLS Epitaxy

Selective epitaxial growth in buried patterns was studied using the vapour-liquid-solid mechanism in Al-Si melt in order to obtain p+-doped SiC localized layers on 4H-SiC substrate. Homogeneous deposition with step bunched morphology was obtained by adding propane at room temperature before growth at 1100°C. Patterns as large as 800 µm and as narrow as 10 µm were completely filled in this way. The deposition kinetics demonstrates that the process is self limited and mainly depends on the initial amount of Si in the liquid. The deposit is highly p-type doped and the p-n junction is demonstrated.

Dilute Aluminium Concentration in 4H-SiC: from SIMS to LTPL Measurements

From a systematic comparison of SIMS measurements with low temperature photoluminescence data, we show that one can directly perform a non destructive (optical) investigation of the residual Al content in 4H-SiC samples. This technique offers the non negligible advantage to be easily extended to Al concentrations below the SIMS detection limit.

Investigation of 3C-SiC(111) Homoepitaxial Growth by CVD at High Temperature

Starting from 3C-SiC(111) layers grown by Vapour-Liquid-Solid mechanism, homoepitaxial growth by Chemical Vapour Deposition was carried out on top of these seeds. The effect of the growth temperature and of the C/Si ratio in the gas phase was investigated on the surface morphology, the roughness and the defect density. It was found that the initial highly step-bunched surface of the VLS seeds could be greatly smoothen using appropriate conditions. These conditions were also found to reduce significantly the defect size and/or density at the surface.

Optical Study of Ge Incorporation in Cubic SiC Layers Grown by VLS

We report an optical study of 3C-SiC layers grown on 6H-SiC substrates by VLS mechanism using a Si-Ge melt. The photoluminescence and μ-Raman results show a clear and significant incorporation of germanium in the layers from the melt. A photoluminescence emission attributed to Ge related transitions is observed in the infrared region. μ-Raman spectra exhibit two peaks related to the Ge-Ge and Si-Ge bonds. From the characteristics of these Raman peaks, it was found that the amount of Ge incorporated inside the 3C layers increases with increasing Ge content of the melt. This has been verified by Particle-Induced X-rays Emission (PIXE) measurements which gave a Ge concentration varying from ~ 1x1019 to ~ 1x1020 at.cm-3. All these results suggest that Ge incorporates in the VLS grown 3C layers by forming Si-Ge-(C) nanoclusters.

Optical Investigation of Stacking Faults and Micro-Crystalline Inclusions In-Low-Doped 4H-SiC Layers

We report a LTPL (Low Temperature PhotoLuminescence) investigation of nominally undoped 4H-SiC epitaxial layers grown on (0001) 4H-SiC substrates. From room temperature Raman spectra, we find evidence of 3C micro-crystalline inclusions (MCIs). From LTPL spectra collected at various distance from the MCIs we find a coexistence of various defects, which behave like quantum wells (QWs) with various effective thickness. Using a 2-dimensional QW approximation we deduce the extent of the perturbation associated with the different defects.

Use of high purity trimethylindium-trimethylamine adduct in MOVPE of InP

Abstract The trimethylindium-trimethylamine adduct was synthesized from indium and methyliodide as starting materials. After purification by zone refining, vapor pressure studies were performed to show its suitability in MOVPE growth of III–V semiconductors. Trimethylindium-trimethylamine was then used to grow InP with both phosphine or bis(phosphinoethane).

Electrical Characterization of PiN Diodes with p+ Layer Selectively Grown by VLS Transport

This paper deals with electrical characterization of PiN diodes fabricated on an 8° off-axis 4H-SiC with a p++ localized epitaxial area grown by Vapour-Liquid-Solid (VLS) transport. It provides for the first time evidence that a high quality p-n junction can be achieved by using this technique followed by a High Temperature Annealing (HTA) process.