Veselko Gustin

An extended ANSI C for processors with a multimedia extension

This paper presents the Multimedia C language, which is designed for the multimedia extensions included in all modern microprocessors. The paper discusses the language syntax, the implementation of its compiler and its use in developing multimedia applications. The goal was to provide programmers with the most natural way of using multimedia processing facilities in the C language. The MMC language has been used to develop some of the most frequently used multimedia kernels. The presented experiments on these scientific and multimedia applications have yielded good performance improvements.

Learning computer architecture concepts with the FPGA-based “Move” microprocessor

In this article we introduce the use of a programmable logic device (PLD) in an application‐oriented study as an example of designing a microprocessor based on reduced instruction set computer (RISC) architecture. Since the concept of an in‐system configurable logic circuit is becoming increasingly popular, we now use it for the purpose of logic design. We suggest that students use PLDs when constructing a central processing unit (CPU) with their own configured functions that are directly implemented in the logic. Such an approach could greatly increase the understanding of the architectural concept of the CPU.

Introducing the vector C

This paper presents the vector C (VC) language, which is designed for the multimedia extensions included in all modern microprocessors. The paper discusses the language syntax, the implementation of its compiler and its use in developing multimedia applications. The goal was to provide programmers with the most natural way of using multi-media processing facilities in the C language. The VC language has been used to develop some of the most frequently used multimedia kernels. The experiments on these scientific and multimedia applications have yielded good performance improvements

Artificial neural network realization with programmable logic circuit

Abstract In this paper some designs of the Boolean Neural Network, as one purely digital class of artificial neural networks, are discused. We concentrate on applications of programmable gate arrays (PGA) programmable logic arrays (PLA), and commercial VLSI circuits. After a precise comparison of various types of neural networks, a programmable cell array (PCA) is proposed, and a 2-dimensiona array of logic and interconnection cell approach is suggested. The structure design of the PCA neural network is presented, and the characteristics of this network are discussed.

Macro Extension for SIMD Processing

The need for multimedia applications has prompted the addition of a SIMD instruction set On the one hand we have modern multimedia execution hardware and on the other we have the software and the general compilers which are not able to automatically exploit the multimedia instruction set. Our solution to these problems is to find statement candidates in the program written in the language C/C++ (as we mainly use this language), and to employ the SIMD instruction set in the easiest possible way. We proposed the algorithm for identifying candidates for parallel processing (ICPP) which is based on the syntax and semantic cheching of statements. We define the macro library MacroVect.c as the substitution for the discovered statement candidates.

Pattern recognition with fuzzy neural network

Abstract This paper explains the character code recognition with the Boolean classifier. The binary values are used both for inputs and outputs, while the learning of the circuit with a set of patterns is done by modified algorithms used in some Boolean neural networks. The use of the fuzzy logic approach offers the possibility of creating a character recognition theory which is fault-tolerant and applicable to all sorts of typefaces and fonts. It provides several examples of patterns scanned with different resolutions and learned with a part of the same set of samples which demonstrates the quality of the fuzzy Boolea classifier.

Fast dependence analysis in a multimedia vectorizing compiler

Summary form only given. There are a number of data dependence tests that have been proposed in the literature. In each test there is a different trade-off between accuracy and efficiency. The most widely used approximate data dependence tests are the Banerjee inequality and the GCD test; whereas the Omega test is a well-known exact data dependence test. We consider parallelization for microprocessors with a multimedia extension (the short SIMD execution model). For the short SIMD parallelism extraction it is essential that, if dependency exists, then the dependence distance is greater than or equal to the number of data processed in the SIMD register. This implies that some loops that could not be vectorized on traditional vector processors can still be parallelized for the short SIMD execution. We present a new data dependence test (D-test) for array references with linear subscripts. Our method extends the Banerjee test in such a way that the dependence analysis will be correct in many cases where dependence exists with the dependence distance that is greater than or equal to the number of data processed in the SIMD register. These special cases in which Banerjee test fails to prove the independence can than be attacked with D-test.

On dependence analysis for SIMD enhanced processors

There are a number of data dependence tests that have been proposed in the literature. In each test there is a different trade-off between accuracy and efficiency. The most widely used approximate data dependence tests are the Banerjee inequality and the GCD test. In this paper we consider parallelization for microprocessors with a multimedia extension (the short SIMD execution model). For the short SIMD parallelism extraction it is essential that, if dependency exists, then the distance between memory references is greater than or equal to the number of data processed in the SIMD register. This implies that some loops that could not be vectorized on traditional vector processors can still be parallelized for the short SIMD execution. In all of these tests the parallelization would be prohibited when actually there is no parallelism restriction relating to the short SIMD execution model. In this paper we present a new, fast and accurate data dependence test (called D-test) for array references with linear subscripts, which is used in a vectorizing compiler for microprocessors with a multimedia extension. The presented test is suitable for use in a dependence analyzer that is organized as a series of tests, progressively increasing in accuracy, as a replacement for the GCD or Banerjee tests.

Realization of multilayer Boolean neural network with logic gate array

Abstract The aim of this paper is to outline a new approach in the digital realization of Boolean Neural Networks. It is based on Programmable Gate Array technology (PGA). Each cell in the gate array performs the binary addition/subtraction function. Space iteration of such digital circuit enables the calculation of all output functions of neurons in the network. the topology of the network influences the connections between neurons and therefore the connections in PGA. This approach offers definite advantages over other solutions. Regular architectures with full connectivity, modularity of completely digital circuits, and possible use of programming support are some of the most important features of the proposed digital realization.

Practical dependence analysis in a SIMD vectorizing compiler

In this paper we present a new, fast and accurate exact data dependence test method with linear cost for array references with linear subscripts, which solves the two-dimensional dependence equation by the use of the Bresenham incremental line algorithm which has been primarily used in computer graphics. The presented method uses only integer calculations and is implemented in our SIMD vectorizing compiler.