Victor Reyes

CASSE: a system-level modeling and design-space exploration tool for multiprocessor systems-on-chip

As SoC complexity grows new methodologies and tools for system design and time-effective ditsign space exploration are required. In this paper we introduce a tool called CASSE, what stands for Camellia system-on-chip simulation environment. CASSE is a fast, flexible, and modular SystemC-based simulation environment which aims to be useful for design-space exploration and system-level design at different abstraction levels. The tool uses transaction-level modeling techniques for fast simulations and easy architectural modeling, and bridge the gap to system implementation by a progressive refinement approach. CASSE is being used in the European 1ST-2001-34410 CAMELLIA project, which focuses on the mapping of innovative smart imaging applications onto an existing video encoding architecture.

A Unified System-Level Modeling and Simulation Environment for MPSoC design: MPEG-4 Decoder Case Study

New generation electronic system-level design tools are the key to overcome the complexity and the increasing design productivity gap in the development of future multiprocessor systems-on-chip. This paper presents a SystemC-based system-level simulation environment, called CASSE, which helps in the modeling and analysis of complex SoCs. CASSE combines application modeling, architecture modeling, mapping and analysis within a unified environment, with the aim to ease and speed up these modeling steps. The main contribution of this tool is to enable this fast modeling and analysis at the very beginning of the design process, helping in the design space exploration phase. CASSE capabilities are disclosed in this work by means of a case study where an MPEG-4 decoder application is implemented on an Altera Excalibur platform

A multicast inter-task communication protocol for embedded multiprocessor systems

Recently, a new programming model and platform interface for MPSoC design and integration called TTL (Task Transaction Level) has been developed and advocated as a standard. In this paper, a specific implementation of the TTL interface named ITCP (Inter-Task Communication Protocol) is presented. ITCP is well suited for both hardware and software implementations and supports features such as multitasking and multicast communication. A configurable SystemC model of the ITCP protocol and its integration in a system-level design methodology is disclosed in this work. Moreover, details of a multi-task ITCP software shell implementation for an ARM9 with eCos RTOS are also given in the paper.

Towards a configurable SoC MPEG-4 advanced simple profile decoder

The evaluation of various architectural designs to allow low bandwidth digital video decoding and reception over the digital audio broadcasting network, and the problem of how to find and implement an optimal HW/SW partition on a Programmable Logic Device with an embedded ARM9 processor are focused. Profiling and design space exploration techniques are applied to the advanced simple profile of an MPEG-4 decoder, for which an innovative SystemC-based system-level design tool, called CASSE, has been used. Simulations results showed that a throughput of 15 QCIF frames per second can be achieved with a low area and low power implementation. Details of this implementation and where the results differ from simulation are presented.

The design of a smart imaging core for automotive and consumer applications: a case study

This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two specific hardware blocks for image processing: a smart imaging coprocessor and an enhanced motion estimator. Both coprocessors have been designed using high-level synthesis tools taking the C programming language as a starting point. The resulting RTL code of each coprocessor has been synthesized and verified on an FPGA board. Two automotive and two mobile smart imaging applications are mapped onto the resulting smart imaging core. This mapping process of the original C++ applications onto the smart imaging core is also presented in this paper.

Automatically Realising Embedded Systems from High-Level Functional Models

To keep pace with the rising computational demands of embedded applications, an effective approach is to raise the level of abstraction at which the design of essential functionality is performed. Raising the level of abstraction allows designers to remove the complexity of low-level and implementation details, thereby gaining design productivity. However, raising the level of abstraction also widens the gap between design and implementation. To overcome the gap between design and implementation, this tutorial demonstrates technologies for

Evaluation of Architectures for an ASP MPEG-4 Decoder Using a System-Level Design Methodology

Trends in multimedia consumer electronics, digital video and audio, aim to reach users through low-cost mobile devices connected to data broadcasting networks with limited bandwidth. An emergent broadcasting network is the digital audio broadcasting network (DAB) which provides CD quality audio transmission together with robustness and efficiency techniques to allow good quality reception in motion conditions. This paper focuses on the system-level evaluation of different architectural options to allow low bandwidth digital video reception over DAB, based on video compression techniques. Profiling and design space exploration techniques are applied over the ASP MPEG-4 decoder in order to find out the best HW/SW partition given the application and platform constraints. An innovative SystemC-based system-level design tool, called CASSE, is being used for modelling, exploration and evaluation of different ASP MPEG-4 decoder HW/SW partitions. System-level trade offs and quantitative data derived from this analysis are also presented in this work.

Signaling in the heterogeneous architecture multiprocessor paradigm

This paper discusses and compares solutions for the issue of signalling and synchronization in the heterogeneous architecture multiprocessor paradigm. The on-chip interconnect infrastructure is split conceptually into a data transport network and a signalling network. This paper presents a SystemC based technique for modelling the communication architecture, with different topologies for the synchronization or signalling network. Each topology is parameterised for several communication requirements that define a point in the communication space. A high abstraction model leads to an experimental set-up that eases the analysis of the quantitative and qualitative behaviour of the networks for representative points in the communication space of the system design. The SystemC simulation models developed allow us to obtain information about total simulation time, processing time spent by the coprocessors, data transport time (read/write) used by the coprocessors (including arbitration time), and synchronization time spent by the coprocessors and the network. Another important metric is the coprocessor usage percentage. Results show that splitting data and signalling networks bring additional improvement to the performance of the system. The model applies well when mapping to architectural platforms the application processes expressed by abstract computational models such as Kahn process networks (KPN), synchronous data flow models (SDF), and generalized communicating sequential processes models (CSP).