Vijay Gangaram

A SMT-based diagnostic test generation method for combinational circuits

A diagnostic test pattern generator using a Satisfiability Modulo Theory (SMT) solver is proposed. Rather than targeting a single fault pair at a time, the proposed SMT approach can distinguish multiple fault pairs in a single instance. Several heuristics are proposed to constrain the SMT formula to further reduce the search space, including fault selection, excitation constraint, reduced primary output vector, and cone-of-influence reduction. Experimental results for the ISCAS85 and full-scan versions of ISCAS89 benchmark circuits show that fewer diagnostic vectors are generated compared with conventional diagnostic test generation methods. Up to 73% reduction in the number of vectors generated can be achieved in large circuits.

Efficient RTL Coverage Metric for Functional Test Selection

For performance-critical microprocessors, efficient test-selection methods are needed for reusing a subset of functional validation tests to detect manufacturing defects. Our new input/output transition fault-coverage metric (TRIO) at the register-transfer level is shown to perform much better than current metric in test selection at only an incrementally higher computational cost. TRIO may also be used for testability analysis early in the design cycle

A Novel SMT-Based Technique for LFSR Reseeding

In order for logic built-in-self-test (LBIST) to achieve coverages comparable with deterministic tests, multiple (and frequently many) seeds are often needed. Unlike previous methods that attempt to chain/compact the number of seeds, we present a novel Satisfiability Modulo Theory (SMT) based technique that can reduce the number of seeds significantly while simultaneously achieving high coverage for LBIST. In this technique we integrate the process of deterministic test generation and seed generation in one SMT process to eliminate the problems of chaining the separately generated deterministic patterns. Experimental results show the promise of the approach.

Functional Test Selection for High Volume Manufacturing

Validation and legacy test suites are often reused for achieving at speed coverage required for testing high frequency semiconductor chips. Porting validation tests to high volume manufacturing (HVM) flows involves extensive manual effort but is required to ensure high quality chips. Functional test selection is the problem of choosing a subset of tests from a large pool of existing tests to maximize the fault coverage while minimizing the test data volume, fault grading time and porting effort. We formulate a framework for test selection that allows various coverage metrics to be used for evaluation. A novel dynamic untestability analysis method is proposed to identify faults that can not be detected by a given test sequence. Conversely this method can be used to compute tight upper bound coverage and hence as a metric for functional test evaluation. Test selection using this new metric gives significant additional fault coverage than toggle based test selection.

Upper bounding fault coverage by structural analysis and signal monitoring

A new algorithm for identifying stuck faults in combinational circuits that cannot be detected by a given input sequence is presented. Other than pre and post-processing steps, certain signal conditions are monitored during logic simulation. These signal conditions are specified by an analysis of dominators and signal reconvergences in the circuit graph. After simulation, a post-processing step identifies faults that cannot be detected by the sequence. For combinational IS GAS benchmarks, the runtime overhead for the algorithm is found to be around 30-40% over that of a logic simulator. Experimental data show a substantial reduction of error in statistical estimates obtained by a stuck-fault coverage estimator when corrected for faults found by this algorithm as guaranteed to be undetected by the given sequence. An effective application of this technique is demonstrated for scan-based test point selection in an industrial scenario where circuit size and vector length prohibit the use of fault simulation

An Efficient 2-Phase Strategy to Achieve High Branch Coverage

We present a new 2-phase symbolic execution driven strategy that achieves high branch coverage in software quickly. Phase 1 follows a greedy approach that quickly covers as many branches as possible by exploring each branch through its corresponding shortest path prefix. Phase 2 covers the remaining branches that are left uncovered if the shortest path to the branch was infeasible. In Phase 1, a basic conflict-driven learning is used to skip all the paths that may have any of the earlier encountered conflicting conditions, while in Phase 2, a more intelligent conflict-driven learning is used to skip regions that do not have a feasible path to any unexplored branch. This results in considerable reduction in unnecessary SMT solver calls. Experimental results show that significant speedup can be achieved, effectively reducing the time to detect a bug and providing higher branch coverage for a fixed time-out period than previous techniques.

Efficient Selection of Observation Points for Functional Tests

The fault coverage of existing functional tests can be enhanced by additional observation points. For a given set of functional tests, this paper proposes an efficient fault-dropping fault simulation method for selecting a subset of observation points at a small fraction of the cost of non-fault-dropping fault simulation. Experimental results on industrial circuits demonstrate the effectiveness of the method in achieving close to optimal results in the size of the selected subset with an order of magnitude less time, without losing achievable coverage. The technique is particularly applicable to industrial designs where fault-simulation times can be prohibitively expensive, even when only a sample of faults is simulated using distributed techniques.

Test generation for circuits with embedded memories using SMT

One of the important challenges in testing modern SOCs is the presence of small embedded memories. These memories are too small to employ memory BIST. Also, making these embedded memories scan-able or employing MBIST would increase the area overhead and/or test application time.

Fast Enhancement of Validation Test Sets to Improve Stuck-at Fault Coverage for RTL circuits

A digital circuit usually comprises a controller and datapath. The time spent for determining a valid controller behavior to detect a fault usually dominates test generation time. A validation test set is used to verify controller behavior and, hence, it activates various controller behaviors. In this paper, we present a methodology wherein the controller behaviors exercised by test sequences in a validation test set are reused for detecting faults in the datapath. A heuristic is used to identify controller behaviors that can justify/propagate pre-computed test vectors/responses of datapath register-transfer level (RTL) modules. Such controller behaviors are said to be compatible with the corresponding pre-computed test vectors/responses. The heuristic is fairly accurate, resulting in the detection of a majority of stuck-at faults in the datapath RTL modules. Also, since test generation is performed at the RTL and the controller behavior is predetermined, test generation time is reduced. For microprocessors, if the validation test set consists of instruction sequences then the proposed methodology also generates instruction-level test sequences