Vijay Sundararajan

Low power synthesis of dual threshold voltage CMOS VLSI circuits

The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1 V and threshold voltage as low as 0.2 V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by up to 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when an arbitrary number of threshold voltages are allowed.

Fast and exact transistor sizing based on iterative relaxation

This paper presents MINFLOTRANSIT, a new transistor sizing tool for fast sizing of combinational circuits with minimal cost. MINFLOTRANSIT is an iterative relaxation-based tool that has two alternating phases. For a circuit with |V| transistors and |E| wires, the first phase (D-phase) is based on minimum cost network flow, which in our application, has a worst case complexity of O(|V/spl par/E| log(log(|V|))). The second phase (W-phase) has a worst case complexity of O(|V/spl par/E|). In practice, during our simulations both the D-phase and W-phase show a near linear run-time dependence on the size of the circuit, comparable to TILOS. Simulation results show excellent run-time behavior for MINFLOTRANSIT on all the ISCAS85 benchmark circuits. For reasonable delay targets, MINFLOTRANSIT shows up to 16.5% area savings (in relatively large circuits) over a circuit sized using a TILOS-like algorithm. In our opinion, the primary contribution of this paper is to take advantage of the structure of the transistor sizing problem and devise an iterative relaxation based gradient descent approach (D-phase) that has excellent convergence properties.

Synthesis of low power folded programmable coefficient FIR digital filters

A novel low-power synthesis technique is presented for the design of folded or time-multiplexed programmable-coefficient FIR filters where storage area is traded-off for lowering power consumption. A systematic technique is developed for low power mapping of FIR filters to architectures with arbitrary number of multipliers and adders. Power consumed in multipliers is reduced by reducing switching activity at both the data-in as well as the coefficient input. Common input operands can be exposed unfolding, which, however leads to a memory Increase. Simulation are obtained for folding 65 and 129 tap bandpass FIR filters. The average power consumed in a multiplier for a fixed number of hardware multipliers with varying unfolding factors is compared. It is observed that most of the gains due to unfolding are obtained for relatively small unfolding factors and therefore for relatively small memory area overhead. Depending on the unfolding factor employed the average power consumed in a multiplier is seen to reduce anywhere from 54.75% to 81.73% when transpose FIR filters are synthesized as opposed to synthesizing direct-form FIR filters with no unfolding.

Energy efficient signaling in deep submicron CMOS technology

In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeater insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeater insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 /spl mu/m, 2.5 V, 6-metal-layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5 V down to 1.5 K.

Synthesis of minimum-area folded architectures for rectangular multidimensional multirate DSP systems

In this paper, we formalize a novel multirate multidimensional folding (MMF) transformation, which is a tool used to systematically synthesize control circuits for pipelined very large scale integrated (VLSI) architectures that implement a restricted but immensely practical class, namely, rectangular decimators/expandors with line-by-line scan, of multirate multidimensional algorithms. Although multirate multidimensional algorithms contain decimators and expanders that change the effective sample rate of a discrete-time signal, it is possible using MMF to time multiplex the algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. MMF constraints are derived, and these constraints are used to address two related issues. The first issue is memory requirements in the folded architectures. We derive expressions for the minimum number of memory units required by a folded architecture that implements a multirate multidimensional algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints that indicate how a multirate multidimensional data flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of DSP applications that are based on multirate multidimensional algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms. Many design examples are considered to demonstrate the viability of MMF. It is shown that MMF is able to save 18-25% area for 1-4 level two-dimensional (2-D) discrete wavelet transforms (DWTs). A tradeoff between computational and storage area is highlighted by our study of a 2064/spl times/2064 4-level 2-D DWT. We also present a few 2-D IIR filter designs, where we are able to exploit the throughput bottleneck of these filters to derive extremely low area designs.

Reducing bus transition activity by limited weight coding with codeword slimming

Transitions on high capacitance busses in VLSI systems result in considerable power dissipation. Various coding schemes have been proposed in literature to encode the input signal in order to reduce the number of transitions. Number of transitions can be reduced by introducing redundancy in data transferred over the busses. For a given amount of redundancy there exists a lower bound on the average number of transitions. In this paper we derive a new coding scheme which leads to extremely practical techniques for bus transmission that reduce bus transitions to within 3.96-8.42% of the lower bound depending on the redundancy employed. There is also a net reduction in power dissipation ranging from 8.53-21.88% over an uncoded bus transmission scheme. This savings in power dissipation is identical to that for bus-invert coding per word transmitted the higher efficiency brought about by codeword slimming, however, results in shorter codewords than bus-invert coding which in turn results in higher energy efficiency in word transmission. Applications suitable for this new technique include systems relying on bit-serial implementation and systems with bit-parallel implementations where the cost of extra parallel-to-serial and serial-to-parallel data-format converters is marginal compared to the power savings obtained.

Synthesis of folded, pipelined architectures for multi-dimensional multirate systems

Motivated by the need for designing efficient architectures for two-dimensional discrete wavelet transforms (DWTs), this paper presents a novel multi-dimensional (MD) folding transformation technique which can be used to synthesize control circuits for pipelined architectures for a specific class of multirate MD digital signal processing (DSP) algorithms. Although a multirate MD DSP algorithm contains decimeters and expanders which change the effective sample rate of a MD discrete time signal, MD folding time-multiplexes the algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single clock signal for the clocking of the datapath. Feasibility constraints are derived for folding a 2-D data-flow graph (DFG) onto a given set of hardware functional units according to a specified schedule. Area/power efficient architectures are derived for 1-4 level 2-D discrete wavelet transforms (DWT) with 18.5-23.3% savings in storage area.

A 64 channel programmable receiver chip for 3G wireless infrastructure

We present a CDMA wireless infrastructure chip that handles digital baseband receive functions for up to 64 voice channels, representing over 150 GOPS of computation, and dissipating 32mW/channel. Vector datapaths and two embedded ARM cores are employed for flexibility and high channel density. The chip is fabricated in a 130 nm 7 layer metal process and contains 75M transistors.

Low power gate resizing of combinational circuits by buffer-redistribution

Low power gate resizing can decrease the power dissipated in a technology mapped circuit while maintaining its critical path. Gate resizing operates as a post-mapping technique for power reduction by replacing some gates, which are faster than necessary, with smaller and slower gates from the underlying gate library. In this paper we propose a new transformation technique for combinational circuits referred to as buffer-redistribution. Buffer-redistribution is then used to model and solve the low-power discrete gate resizing problem in an exact manner in polynomial time and in a noniterative fashion for a complete gate library. Suboptimal solutions are obtained with incomplete gate libraries. In contrast past polynomial time techniques for gate resizing were either based on heuristics or based on much slower iterative exact algorithms. Simulation results on ISCAS85 benchmark circuits demonstrate 2.1%-54.1% power reduction based on the proposed buffer-redistribution based low-power gate resizing. Power savings from 0%-44.13% are demonstrated over the same circuits mapped for minimum area. The time required for resizing varies from 2.77s-1256.76s.

Efficient pseudo-noise sequence generation for spread-spectrum applications

Novel approaches for linear feedback shift register based pseudo noise generators are presented. Area-delay tradeoff between the various approaches is also presented. The principal approaches that are studied in this paper include 1) State-transition matrix based approaches, 2) State-transition matrix based approaches with lookahead, 3) State storage based approaches and 4) Polynomial multiplication based approaches. Synthesis results are also provided to illustrate the area/delay trade-offs.