Vikas Jha

A unified framework for conservative and optimistic distributed simulation

A great deal of research in the area of distributed discrete event simulation has focussed on evaluating the performance of variants of conservative and optimistic methods on different types of applications. Application characteristics like lookahead, communication patterns, etc. have been found to affect the suitability of a specific protocol to simulate a given model. For many systems, it may be the case that different subsystems possess contradictory characteristics such that whereas some subsystems may be simulated efficiently using a conservative protocol, others may be more amenable to optimistic methods. Furthermore, the suitability of a protocol for a given subsystem may change dynamically. We propose a parallel simulation protocol that allows different parts of a system to be simulated using different protocols, allowing these protocols to be switched dynamically. A proof of correctness is presented, along with some preliminary performance discussion.

Transparent implementation of conservative algorithms in parallel simulation languages

Parallel discrete event simulation offers significant speedup over the traditional sequential event list algorithm. A number of conservative and optimistic algorithms have been proposed and studied for parallel simulation. We examine the problem of transparent execution of a simulation model using conservative algorithms, and present experimental results on the performance of these transparent implementations. The conservative algorithms implemented and compared include the null message algorithm, the conditional-event algorithm, and a new algorithm which is a combination of these. We describe how dynamic topology can be supported by conservative algorithms. Language constructs to express lookahead are discussed. Finally, performance measurements on a variety of benchmarks are presented, along with a study of the relationship between model characteristics like lookahead, communication topology and the performance of conservative algorithms.

Parallel simulation environment for mobile wireless networks

A parallel simulator has been designed for the evaluation of wireless, multihop, mobile networks. This paper describes the process of porting the simulator from a sequential to a parallel environment. Parallelization is critical in large radio networks, where the complexity of radio propagation models, channel access schemes and interference patterns makes sequential simulation very time consuming - in the order of several hours for 100 nodes experiments. With parallel execution, speedups of up to tenfold have been observed on a 16 processor SP/2, making large net work simulations viable.

Simultaneous events and lookahead in simulation protocols

A discrete event simulation model may contain several events that have the same timestamp, referred to as simultaneous events. In general, the results of a simulation depend on the order in which simultaneous events are executed. Simulation languages and protocols use different, sometimes ad hoc, tie-breaking mechanisms to order simulataneous events. As a result, it may be impossible to reproduce the results of a simulation model across different simulators. This article presents a systematic analysis of the lookahead requirements for sequential and parallel simulation protocols, utilizing the process-oriented world view, with respect to their abililty to execute models with simultaneous events in a deterministic order. In particular, the article shows that most protocols, including the global event list protocol and commonly used parallel conservative and optimistic protocols, require that the simulation model provide some form of lookahead guarantee to enforce deterministc ordering of simultaneous events. The article also shows that the lookahead requirements for many protocols can be weakened if the model allows simultaneous events to be processed in a nondeterministic order. Finally, the lookahead properties that must be satisfied by a model in order for its execution to make guaranteed progress are derived using various simulation protocols.

A performance evaluation methodology for parallel simulation protocols

Most experimental studies of the performance of parallel simulation protocols use speedup or number of events processed per unit time as the performance metric. Although helpful in evaluating the usefulness of parallel simulation for a given simulation model, these metrics tell us little about the efficiency of the simulation protocol used. In this paper, we describe an Ideal Simulation Protocol (ISP), based on the concept of critical path, which experimentally computes the best possible execution time for a simulation model on a given parallel architecture. Since ISP computes the bound by actually executing the model on the given parallel architecture, it is much more realistic than that computed by a uniprocessor critical path analysis. The paper illustrates, using parameterized synthetic benchmarks, how an ISP-based performance evaluation can lead to much better insights into the performance of parallel simulation protocols than what would be gained from speedup graphs alone.

A multidimensional study on the feasibility of parallel switch-level circuit simulation

This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: (i) parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes, (ii) evaluating effectiveness of several partitioning algorithms for parallel simulation, and (iii) demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3K transistors to about 87K transistors.

Parallel gate-level circuit simulation on shared memory architectures

This paper presents the results of an experimental study to evaluate the effectiveness of parallel simulation in reducing the execution time of gate-level models of VLSI circuits. Specific contributions of this paper include (i) the design of a gate-level parallel simulator that can be executed, without any changes on both distributed memory and shared memory parallel architectures, (ii) demonstrated speedups with both conservative and optimistic simulation protocols (almost all previous studies on circuit simulation have failed to extract speedups with conservative protocols); in particular we showed that a speedup of about 3 was obtained on 8 processors of Sparc1000 for conservative algorithms and about 2 for optimistic algorithms for circuits in the ISCAS85 benchmark suite; and (iii) performance comparison between shared memory and distributed memory implementations of the simulator.

Parallel logic level simulation of VLSI circuits

Interest in the exploitation of parallelism in circuit simulation has been increasing steadily. In this paper, we study parallel logic level simulation of combinational VLSI Boolean networks using both conservative and optimistic simulation algorithms. In particular, we describe a logic level circuit simulator that uses an acyclic multi-way network partitioning algorithm to decompose Boolean networks and an algorithm-independent simulation language that allows a discrete-event simulation model to be executed using a variety of simulation algorithms. The simulator has been implemented on an IBM SP1 supercomputer and was used to simulate a set of combinational Boolean circuits from the ISCAS85 benchmark suite. Our results show that it is feasible to obtain speedups for even relatively small circuits using both conservative and optimistic methods.

The Maisie environment for parallel simulation

Maisie is among the few languages that separates the simulation program from the underlying algorithm (sequential or parallel) that is used to execute the program. It is thus possible to design a sequential simulation and, if needed, to subsequently port it to a parallel machine for execution with optimistic or conservative algorithms. We provide an overview of the Maisie simulation environment and present experimental measurements of a model with both conservative and optimistic parallel algorithms. We also describe our current work in adding inheritance to the Maisie language.<<ETX>>