Vincent Néri

XtremWeb: a generic global computing system

Global computing achieves high throughput computing by harvesting a very large number of unused computing resources connected to the Internet. This parallel computing model targets a parallel architecture defined by a very high number of nodes, poor communication performance and continuously varying resources. The unprecedented scale of the global computing architecture paradigm requires us to revisit many basic issues related to parallel architecture programming models, performance models, and class of applications or algorithms suitable for this architecture. XtremWeb is an experimental global computing platform dedicated to provide a tool for such studies. The paper presents the design of XtremWeb. Two essential features of this design are multi-applications and high-performance. Accepting multiple applications allows institutions or enterprises to set up their own global computing applications or experiments. High-performance is ensured by scalability, fault tolerance, efficient scheduling and a large base of volunteer PCs. We also present an implementation of the first global application running on XtremWeb.

XtremWeb: Building an Experimental Platform for Global Computing

Global Computing achieves highly distributed computations by harvesting a very large number of unused computing resources connected to the Internet. Although the basic techniques for Global Computing are well understood, several issues remain unadressed, such as the ability to run a large variety of applications, economical models for resource management, performance models accounting for WAN and machine components, and finally new parallel algorithms based on true massive parallelism, with very limited, if any, communication capability. The main purpose of XtremWeb is to build a platform to explore the potential of Global Computing. This paper presents the design decisions of the first implementation of XtremWeb. We also present some early performance measurement, mostly to highlight that even some basic performance features are not well understood yet.

XtremWeb & Condor : sharing resources between Internet connected Condor pool

Grid computing presents two major challenges for deploying large scale applications across wide area networks gathering volunteers PC and clusters/parallel computers as computational resources: security and fault tolerance. This paper presents a lightweight Grid solution for the deployment of multi-parameters applications on a set of clusters protected by firewalls. The system uses a hierarchical design based on Condor for managing each cluster locally and XtremWeb for enabling resource sharing among the clusters. We discuss the security and fault tolerance mechanisms used for this design and demonstrate the usefulness of the approach measuring the performances of a multi-parameters bio-chemistry application deployed on two sites: University of Wisconsin/Madison and Paris South University. This experiment shows that we can efficiently and safely harness the computational power of about 200 PC distributed on two geographic sites.

Scalability Comparison of Four Host Virtualization Tools

Virtualization tools are becoming popular in the context of Grid Computing because they allow running multiple operating systems on a single host and provide a confined execution environment. In several Grid projects, virtualization tools are envisioned to run many virtual machines per host. This immediately raises the issue of virtualization scalability.In this paper, we compare the scalability merits of Four virtualization tools. First, from a simple experiment, we motivate the need for simple microbenchmarks. Second, we present a set of metrics and related methodologies. We propose four microbenchmarks to measure the different scalability parameters for the different machine resources (CPU, memory disk and network) on three scalability metrics (overhead, linearity and isolation). Third, we compare four virtual machine technologies (Vserver, Xen, UML and VMware). The results of this study demonstrate that all the compared tools present different behaviors with respect to scalability, in terms of overhead, resource occupation and isolation. Thus this work will help user to select tools according to their application characteristics.

Balanced Distributed Memory Parallel Computers

Mismatches between on-chip high performance CPU and data access times is the basic reason for the increasing gap between peak and sustained performance in distributed memory parallel computers. We propose the concept of balanced architectures, based on a network with a dynamic topology and communication patterns determined at compile time. The corresponding processing element is a cacheless CPU, which can achieve a 1 FLOP/clock cycle rate. Network and PE features are presented. An example shows that balanced architectures keep efficiency when scaling.

4-valued BiCMOS circuits for the transmission system of a massively parallel architecture

Two versions of four-valued encoder and decoder circuits using a BiCMOS technology are presented. A comparison is made of the performance of CMOS-only and BiCMOS versions of these circuits. Such circuits are intended for use in a four-valued transmission system in the 3D interconnection network of a massively parallel architecture. The main difference in performance between the two versions comes from the use of BiCMOS encoder circuits. As expected, the bipolar transistor that is used gives a significant reduction in chip area (from 20500 lambda /sup 2/ to 11300 lambda /sup 2/). For the entire transmission path, the BiCMOS version has an equivalent propagation delay for the evaluation phase and an improved delay for the precharge phase (3.8 ns instead of 13.2 ns). The total active chip area is reduced by 28%. The advantage of the BiCMOS encoder circuit comes from the decoupling of the process of generation of the four different levels realized by the MOS transistors and that of driving the high-capacitance load. BiCMOS technologies give new circuitry perspectives for four-valued off-chip transmission.<<ETX>>

Hardware features of the static communication network of a parallel architecture

Abstract We present the hardware features of a communication network which has been designed for compiled communication schemes. It is based on a high speed serial link crossbar switch and a Clos-like interconnection network.

VLSI Design of a 3-D Highly Parallel Message-Passing Architecture

We study the feasibility of a massively parallel architecture, the Mega machine, intended for demand-driven and message-passing functional programming. Mega holds thousands of Processing Elements (PE) and may execute millions of parallel functional processes.

Java-based coupling for parallel predictive-adaptive domain decomposition

Adaptive domain decomposition exemplifies the problem of integrating heterogeneous software components with intermediate coupling granularity. This paper describes an experiment where a data-parallel (HPF) client interfaces with a sequential computation server through Java. We show that seamless integration of data-parallelism is possible, but requires most of the tools from the Java palettec Java Native Interface (JNI), Remote Method Invocation (RMI), callbacks and threads.