Vinod John

Filter Optimization for Grid Interactive Voltage Source Inverters

Higher order LCL filters are essential in meeting the interconnection standard requirement for grid-connected voltage source converters. LCL filters offer better harmonic attenuation and better efficiency at a smaller size when compared to the traditional L filters. The focus of this paper is to analyze the LCL filter design procedure from the point of view of power loss and efficiency. The IEEE 1547-2008 specifications for high-frequency current ripple are used as a major constraint early in the design to ensure that all subsequent optimizations are still compliant with the standards. Power loss in each individual filter component is calculated on a per-phase basis. The total inductance per unit of the LCL filter is varied, and LCL parameter values which give the highest efficiency while simultaneously meeting the stringent standard requirements are identified. The power loss and harmonic output spectrum of the grid-connected LCL filter is experimentally verified, and measurements confirm the predicted trends.

High-performance active gate drive for high-power IGBT's

This paper deals with an active gate drive (AGD) technology for high power IGBTs. It is based on an optimal combination of several requirements necessary for good switching performance under hard switching conditions. The scheme specifically combines together the slow drive requirements for low noise and switching stress and the fast drive requirements for high speed switching and low switching energy loss. The gate drive can also effectively dampen oscillations during low current turn-on transients in the IGBT. This paper looks at the conflicting requirements of the conventional gate drive circuit design and demonstrates, using experimental results, that the proposed three-stage active gate drive technique can be an effective solution.

Investigation of anti-islanding protection of power converter based distributed generators using frequency domain analysis

The anti-islanding algorithm proposed by the Sandia national laboratories is analyzed in this study because this scheme, also known as the Sandia scheme, is considered to be effective in detecting islanding of distributed generation systems. Previously, other than heuristic approaches, there has not been any quantitative analysis for tuning the control gains of the algorithm based on the power rating and bandwidth of the distributed generation (DG) power converter. The paper interprets the components of the algorithm that affect the voltage magnitude and frequency into block diagrams that can be linearized and studied using continuous time approximations. This paper uses a frequency domain approach to analyze the range for the gains required by anti-islanding algorithm to effectively determine the disconnection of the mains grid within an acceptable time duration. The analysis provides guidelines for using Sandias national laboratory schemes under different application conditions. The results are validated using detailed time domain DG and power system simulations.

Mitigation of Lower Order Harmonics in a Grid-Connected Single-Phase PV Inverter

In this paper, a simple single-phase grid-connected photovoltaic (PV) inverter topology consisting of a boost section, a low-voltage single-phase inverter with an inductive filter, and a step-up transformer interfacing the grid is considered. Ideally, this topology will not inject any lower order harmonics into the grid due to high-frequency pulse width modulation operation. However, the nonideal factors in the system such as core saturation-induced distorted magnetizing current of the transformer and the dead time of the inverter, etc., contribute to a significant amount of lower order harmonics in the grid current. A novel design of inverter current control that mitigates lower order harmonics is presented in this paper. An adaptive harmonic compensation technique and its design are proposed for the lower order harmonic compensation. In addition, a proportional-resonant-integral (PRI) controller and its design are also proposed. This controller eliminates the dc component in the control system, which introduces even harmonics in the grid current in the topology considered. The dynamics of the system due to the interaction between the PRI controller and the adaptive compensation scheme is also analyzed. The complete design has been validated with experimental results and good agreement with theoretical analysis of the overall system is observed.

Fast-clamped short-circuit protection of IGBT's

Identification of fault current during the operation of a power semiconductor switch and activation of suitable remedial actions are important for reliable operation of power converters. A short circuit is a basic and severe fault situation in a circuit structure, such as voltage-source converters. This paper presents a new active protection circuit for fast and precise clamping and safe shutdown of fault currents of the insulated gate bipolar transistors (IGBTs). This circuit allows operation of the IGBTs with a higher on-state gate voltage, which can thereby reduce the conduction loss in the device without compromising the short-circuit protection characteristics. The operation of the circuit is studied under various conditions, considering variation of temperature, rising rate of fault current, gate voltage value and protection circuit parameters. An evaluation of the operation of the circuit is made using IGBTs from different manufacturers to confirm the effectiveness of the protection circuit.

Common-Mode Filter Design for PWM Rectifier-Based Motor Drives

A common-mode (CM) filter based on the LCL filter topology is proposed in this paper, which provides a parallel path for ground currents and which also restricts the magnitude of the EMI noise injected into the grid. The CM filter makes use of the components of a line to line LCL filter, which is modified to address the CM voltage with minimal additional components. This leads to a compact filtering solution. The CM voltage of an adjustable speed drive using a PWM rectifier is analyzed for this purpose. The filter design is based on the CM equivalent circuit of the drive system. The filter addresses the adverse effects of the PWM rectifier in an adjustable speed drive. Guidelines are provided on the selection of the filter components. Different variants of the filter topology are evaluated to establish the effectiveness of the proposed circuit. Experimental results based on EMI measurement on the grid side and the CM current measurement on the motor side are presented. These results validate the effectiveness of the filter.

Investigation of antiislanding protection of power converter based distributed generators using frequency domain analysis

Islanding of a grid connected distributed generation (DG) unit occurs when a section of the utility system containing such generators is disconnected from the main utility, but the independent DGs continue to energize the utility lines in the isolated section (termed as an island). Unintended islanding is a concern, primarily because it poses a hazard to utility and customer equipment, maintenance personnel and the general public. The algorithm proposed by the Sandia National Laboratories is analyzed in this study because it is considered to be effective in detecting the formation of such islands. Previously, there has not been any quantitative analysis for tuning the control gains of the algorithm based on the rating and bandwidth of the DG power converter. The paper interprets the components of the algorithm that affect the voltage magnitude and frequency into block diagrams that can be linearized and studied using continuous time approximations. The model represents DG operation while connected or disconnected from the main utility. This paper uses frequency domain approach to analyze the range for the gains required by antiislanding algorithm to effectively determine the disconnection of the mains grid within an acceptable time duration. The effect of variation of DGs operating power level is studied and demonstrated how the gains of the algorithm can be set to be effective for a wide power range. The results are validated using detailed time domain DG and power system simulations.

A novel design method for SOGI-PLL for minimum settling time and low unit vector distortion

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

Analysis of Bandwidth–Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

Development of a High-Speed Static Switch for Distributed Energy and Microgrid Applications

Distributed energy resources can provide power to local loads in the electric distribution system and benefits such as improved reliability. Microgrids are intentional islands formed at a facility or in an electrical distribution system that contains at least one distributed resource and associated loads. Microgrids that operate both electrical generation and loads in a coordinated manner can offer additional benefits to the customer and local utility. The loads and energy sources can be disconnected from and reconnected to the area or local utility with minimal disruption to the local loads, thereby improving reliability. This paper details the development and testing of a highspeed static switch for distributed energy and microgrid applications.